DP MST DSC dock unable to reach resolution/freq that require DSC on Meteor Lake

The dock (website does advertise support for Android/Linux/Chrome OS) so i thought the compatibility would be "good". https://i-tec.pro/wp-content/uploads/datasheety/C31NANOHDM2DOCPD_en.pdf

I am currently unsure if i am dealing with a dock compatibility problem or i915 problem since meteor lake is still relatively new, if you could point me to the right direction i would appreciate it.

The dock works as advertised in windows on the same hardware (i am able to run 2 external HDMI displays at 1440p@144Hz).
The best i can do in linux is 1x 1440p@100Hz + 1x 1440p@60hz, trying to select higher refresh rate (which does show up in the ui/dropdowns) does "nothing".
Additional odd thing is, that even having a single display connected here, 1440p@120Hz nor 1440p@144Hz would properly apply (there should be enough bandwidth to run it anyway)?
If i would set both to 100 Hz for example and disconnect/reconnect the dock one of the monitors would not initialize/ends up being dark.

I am on Fedora 40 + wayland, so no xrand output (dunno if there is an xrandr equivalent i could use/post here?) Linux version 6.10.0-rc7-stefan+ i used the latest available drm tip at the time of writing

Date:   Thu Jul 25 13:17:24 2024 -0700
commit 1c38b092d18ce973d9ec31a4ab097fbc344ab8f2
drm-tip: 2024y-07m-25d-20h-16m-42s UTC integration manifest

00:02.0 VGA compatible controller [0300]: Intel Corporation Meteor Lake-P [Intel Arc Graphics] [8086:7d55] (rev 08) (prog-if 00 [VGA controller])
	Subsystem: Lenovo Device [17aa:3803]
	Flags: bus master, fast devsel, latency 0, IRQ 161, IOMMU group 0
	Memory at 4818000000 (64-bit, prefetchable) [size=16M]
	Memory at 4000000000 (64-bit, prefetchable) [size=256M]
	Expansion ROM at 000c0000 [virtual] [disabled] [size=128K]
	Capabilities: [40] Vendor Specific Information: Len=0c <?>
	Capabilities: [70] Express Root Complex Integrated Endpoint, IntMsgNum 0
	Capabilities: [ac] MSI: Enable+ Count=1/1 Maskable+ 64bit+
	Capabilities: [d0] Power Management version 3
	Capabilities: [100] Null
	Capabilities: [110] Process Address Space ID (PASID)
	Capabilities: [200] Address Translation Service (ATS)
	Capabilities: [420] Physical Resizable BAR
	Capabilities: [320] Single Root I/O Virtualization (SR-IOV)
	Capabilities: [400] Latency Tolerance Reporting
	Kernel driver in use: i915
	Kernel modules: i915, xe

Full (had to go with 8M buffer) dmesg.log

I tried to isolate the log a little bit to a place where i tried to apply above 60 Hz refresh rate (which didn't take effect). dmesg_later.log

The below section does mention DSC off (although i am not sure how to interpret it)

[  262.358282] i915 0000:00:02.0: [drm:drm_dp_mst_duplicate_state [drm_display_helper]] port 000000005f4bcd6d (4)
[  262.358328] i915 0000:00:02.0: [drm:drm_dp_mst_duplicate_state [drm_display_helper]] port 000000008018ace1 (4)
[  262.358374] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:300:DP-6] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
[  262.358731] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:277:DDI TC3/PHY TC3][CRTC:82:pipe A] DP link limits: pixel clock 497750 kHz DSC off max lanes 2 max rate 810000 max pipe_bpp 24 max link_bpp 24.0000
[  262.358973] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Looking for slots in range min bpp 18 max bpp 24
[  262.359294] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Trying bpp 24
[  262.359612] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Got 60 slots for pipe bpp 24 dsc 0
[  262.359926] [drm:intel_dp_mst_compute_config [i915]] 8b/10b encoding format on mst_state 0x00000000928ecfbf
[  262.360218] i915 0000:00:02.0: [drm:intel_dp_mst_compute_config [i915]] PSR disabled by flag
[  262.360542] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:82:pipe A] hw max bpp: 30, pipe bpp: 24, dithering: 0
[  262.360860] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:298:DP-5] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
[  262.361070] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:277:DDI TC3/PHY TC3][CRTC:134:pipe B] DP link limits: pixel clock 410500 kHz DSC off max lanes 2 max rate 810000 max pipe_bpp 24 max link_bpp 24.0000
[  262.361202] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Looking for slots in range min bpp 18 max bpp 24
[  262.361292] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Trying bpp 24
[  262.361380] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Got 50 slots for pipe bpp 24 dsc 0
[  262.361467] [drm:intel_dp_mst_compute_config [i915]] 8b/10b encoding format on mst_state 0x00000000928ecfbf
[  262.361558] i915 0000:00:02.0: [drm:intel_dp_mst_compute_config [i915]] PSR disabled by flag
[  262.361646] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:134:pipe B] hw max bpp: 30, pipe bpp: 24, dithering: 0
[  262.361759] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:300:DP-6] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
[  262.361870] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:82:pipe A] Link bpp limited to 23.9375
[  262.361986] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:277:DDI TC3/PHY TC3][CRTC:82:pipe A] DP link limits: pixel clock 497750 kHz DSC off max lanes 2 max rate 810000 max pipe_bpp 24 max link_bpp 18.0000
[  262.362077] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Looking for slots in range min bpp 18 max bpp 18
[  262.362163] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Trying bpp 18
[  262.362248] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Got 46 slots for pipe bpp 18 dsc 0
[  262.362331] [drm:intel_dp_mst_compute_config [i915]] 8b/10b encoding format on mst_state 0x00000000928ecfbf
[  262.362417] i915 0000:00:02.0: [drm:intel_dp_mst_compute_config [i915]] PSR disabled by flag
[  262.362502] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:82:pipe A] hw max bpp: 30, pipe bpp: 18, dithering: 1
[  262.362612] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:298:DP-5] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
[  262.362720] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:277:DDI TC3/PHY TC3][CRTC:134:pipe B] DP link limits: pixel clock 410500 kHz DSC off max lanes 2 max rate 810000 max pipe_bpp 24 max link_bpp 24.0000
[  262.362810] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Looking for slots in range min bpp 18 max bpp 24
[  262.362898] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Trying bpp 24
[  262.362984] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Got 50 slots for pipe bpp 24 dsc 0
[  262.363070] [drm:intel_dp_mst_compute_config [i915]] 8b/10b encoding format on mst_state 0x00000000928ecfbf
[  262.363160] i915 0000:00:02.0: [drm:intel_dp_mst_compute_config [i915]] PSR disabled by flag
[  262.363246] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:134:pipe B] hw max bpp: 30, pipe bpp: 24, dithering: 0
[  262.363358] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:300:DP-6] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
[  262.363467] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:82:pipe A] Link bpp limited to 23.9375
[  262.363575] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:277:DDI TC3/PHY TC3][CRTC:82:pipe A] DP link limits: pixel clock 497750 kHz DSC off max lanes 2 max rate 810000 max pipe_bpp 24 max link_bpp 18.0000
[  262.363666] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Looking for slots in range min bpp 18 max bpp 18
[  262.363751] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Trying bpp 18
[  262.363835] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Got 46 slots for pipe bpp 18 dsc 0
[  262.363929] [drm:intel_dp_mst_compute_config [i915]] 8b/10b encoding format on mst_state 0x00000000928ecfbf
[  262.364016] i915 0000:00:02.0: [drm:intel_dp_mst_compute_config [i915]] PSR disabled by flag
[  262.364102] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:82:pipe A] hw max bpp: 30, pipe bpp: 18, dithering: 1
[  262.364215] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:298:DP-5] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
[  262.364326] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:134:pipe B] Link bpp limited to 23.9375
[  262.364437] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:277:DDI TC3/PHY TC3][CRTC:134:pipe B] DP link limits: pixel clock 410500 kHz DSC off max lanes 2 max rate 810000 max pipe_bpp 24 max link_bpp 18.0000
[  262.364526] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Looking for slots in range min bpp 18 max bpp 18
[  262.364613] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Trying bpp 18
[  262.364699] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Got 38 slots for pipe bpp 18 dsc 0
[  262.364785] [drm:intel_dp_mst_compute_config [i915]] 8b/10b encoding format on mst_state 0x00000000928ecfbf
[  262.364872] i915 0000:00:02.0: [drm:intel_dp_mst_compute_config [i915]] PSR disabled by flag
[  262.364966] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:134:pipe B] hw max bpp: 30, pipe bpp: 18, dithering: 1
[  262.365079] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:300:DP-6] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
[  262.365190] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:82:pipe A] Link bpp limited to 17.9375
[  262.365300] i915 0000:00:02.0: [drm:intel_dp_mst_compute_config [i915]] Try DSC (fallback=no, joiner=no, force=no)
[  262.365390] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [ENCODER:279:DP-MST A] config failure: -22
[  262.365500] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:300:DP-6] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
[  262.365610] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:82:pipe A] Link bpp limited to 23.9375
[  262.365718] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:277:DDI TC3/PHY TC3][CRTC:82:pipe A] DP link limits: pixel clock 497750 kHz DSC off max lanes 2 max rate 810000 max pipe_bpp 24 max link_bpp 18.0000
[  262.365808] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Looking for slots in range min bpp 18 max bpp 18
[  262.365899] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Trying bpp 18
[  262.365984] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Got 46 slots for pipe bpp 18 dsc 0
[  262.366071] [drm:intel_dp_mst_compute_config [i915]] 8b/10b encoding format on mst_state 0x00000000928ecfbf
[  262.366157] i915 0000:00:02.0: [drm:intel_dp_mst_compute_config [i915]] PSR disabled by flag
[  262.366242] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:82:pipe A] hw max bpp: 30, pipe bpp: 18, dithering: 1
[  262.366354] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:298:DP-5] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
[  262.366464] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:134:pipe B] Link bpp limited to 23.9375
[  262.366575] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:277:DDI TC3/PHY TC3][CRTC:134:pipe B] DP link limits: pixel clock 410500 kHz DSC off max lanes 2 max rate 810000 max pipe_bpp 24 max link_bpp 18.0000
[  262.366668] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Looking for slots in range min bpp 18 max bpp 18
[  262.366755] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Trying bpp 18
[  262.366841] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Got 38 slots for pipe bpp 18 dsc 0
[  262.366937] [drm:intel_dp_mst_compute_config [i915]] 8b/10b encoding format on mst_state 0x00000000928ecfbf
[  262.367025] i915 0000:00:02.0: [drm:intel_dp_mst_compute_config [i915]] PSR disabled by flag
[  262.367112] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:134:pipe B] hw max bpp: 30, pipe bpp: 18, dithering: 1
[  262.367247] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:300:DP-6] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
[  262.367440] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:82:pipe A] Link bpp limited to 23.9375
[  262.367567] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:277:DDI TC3/PHY TC3][CRTC:82:pipe A] DP link limits: pixel clock 497750 kHz DSC off max lanes 2 max rate 810000 max pipe_bpp 24 max link_bpp 18.0000
[  262.367671] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Looking for slots in range min bpp 18 max bpp 18
[  262.367763] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Trying bpp 18
[  262.367853] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Got 46 slots for pipe bpp 18 dsc 0
[  262.367947] [drm:intel_dp_mst_compute_config [i915]] 8b/10b encoding format on mst_state 0x00000000928ecfbf
[  262.368038] i915 0000:00:02.0: [drm:intel_dp_mst_compute_config [i915]] PSR disabled by flag
[  262.368127] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:82:pipe A] hw max bpp: 30, pipe bpp: 18, dithering: 1
[  262.368251] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:298:DP-5] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
[  262.368371] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:134:pipe B] Link bpp limited to 17.9375
[  262.368490] i915 0000:00:02.0: [drm:intel_dp_mst_compute_config [i915]] Try DSC (fallback=no, joiner=no, force=no)
[  262.368569] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [ENCODER:280:DP-MST B] config failure: -22
[  262.368675] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:300:DP-6] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
[  262.368781] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:82:pipe A] Link bpp limited to 23.9375
[  262.368890] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:277:DDI TC3/PHY TC3][CRTC:82:pipe A] DP link limits: pixel clock 497750 kHz DSC off max lanes 2 max rate 810000 max pipe_bpp 24 max link_bpp 18.0000
[  262.368975] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Looking for slots in range min bpp 18 max bpp 18
[  262.369053] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Trying bpp 18
[  262.369131] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Got 46 slots for pipe bpp 18 dsc 0
[  262.369208] [drm:intel_dp_mst_compute_config [i915]] 8b/10b encoding format on mst_state 0x00000000928ecfbf
[  262.369285] i915 0000:00:02.0: [drm:intel_dp_mst_compute_config [i915]] PSR disabled by flag
[  262.369363] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:82:pipe A] hw max bpp: 30, pipe bpp: 18, dithering: 1
[  262.369483] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:298:DP-5] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
[  262.369684] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:134:pipe B] Link bpp limited to 23.9375
[  262.369866] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:277:DDI TC3/PHY TC3][CRTC:134:pipe B] DP link limits: pixel clock 410500 kHz DSC off max lanes 2 max rate 810000 max pipe_bpp 24 max link_bpp 18.0000
[  262.370034] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Looking for slots in range min bpp 18 max bpp 18
[  262.370180] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Trying bpp 18
[  262.370320] i915 0000:00:02.0: [drm:intel_dp_mst_find_vcpi_slots_for_bpp.isra.0 [i915]] Got 38 slots for pipe bpp 18 dsc 0

Any help would be greatly appreciated, thank you.

Edited Jul 26, 2024 by Stefan

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DP MST DSC dock unable to reach resolution/freq that require DSC on Meteor Lake