Kernel 5.1-5.3 MCLK stuck at 167MHz Vega 10 (56/64)
Submitted by Anton Herzfeld
Assigned to Alex Deucher @agd5f
Link to original bug (#110777)
Description
Hi,
Since Kernel 5.1 up-to Kernel 5.2 my Vega 56 card's memory clock is stuck at 167MHz and does not boost up any more.
The exact same setup boosts fine to 1000MHz memclk when running Kernel 5.0.13.
Is there any info I can provide to get this fixed?
Activity
The issue is fully fixed on kernel master (currently I am using commit 460b48a0fefce25beb0fc0139e721c5691d65d7f) when reverting drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c back to the state it was around kernel 5.0.13.
https://git.archlinux.org/linux.git/tree/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c?h=v5.0.13-arch1
I will start bisecting soon to figure out the exact commit that has caused the issue.reverting the following two patches fixes the boost in memory clocks but it seems once mem clock has ramped up it's not going down again.
1.
Revert "drm/amd/powerplay: update soc boot and max level on vega10"
This reverts commit 373e87fc91527124cb8ec21465a6d070a65c56af.
2.
Revert "drm/amd/powerplay: support Vega10 SOCclk and DCEFclk dpm level settings"
This reverts commit bb05821b13fa0c0b97760cb292b30d3105d65954.
Evan Quan evan.quan@amd.com
Alex Deucher alexander.deucher@amd.comThe following patch fixes the issue with boosting again:
https://cgit.freedesktop.org/~agd5f/linux/commit/drivers/gpu/drm/amd/powerplay/hwmgr?h=amd-staging-drm-next&id=7d59c41b5150d0641203f91cfcaa0f9af5999cce
however it also seems to expose the issue in mclk not going down again once it has boosted.
just to clarify the issue occurs when using manual OD on mclk since kernel 5.1.@alex Deucher is there any chance we can get a backport of https://cgit.freedesktop.org/~agd5f/linux/commit/drivers/gpu/drm/amd/powerplay/hwmgr?h=amd-staging-drm-next&id=7d59c41b5150d0641203f91cfcaa0f9af5999cce
into the 5.1 Kernel? This Kernel is broken for Vega 10 otherwise (Kernel 5.2 is also still broken).I have to confirm this issue with kernel 5.2.
HBM2 clocks are at 167MHz if i try to overclock memory via write to:
/sys/class/drm/card0/device/pp_od_clk_voltage or
/sys/class/drm/card0/device/pp_table
Bellow is an output of a monitoring script:
gpu_vdd: 1100 gpu_clk: 1638000000 mem_clk: 167000000 temp: 40000 fan: 1625 pwm: 109 pow: 165000000
gpu_vdd: 1100 gpu_clk: 1623000000 mem_clk: 167000000 temp: 39000 fan: 1608 pwm: 109 pow: 162000000
gpu_vdd: 1100 gpu_clk: 1637000000 mem_clk: 167000000 temp: 41000 fan: 1603 pwm: 109 pow: 161000000
gpu_vdd: 1100 gpu_clk: 1639000000 mem_clk: 167000000 temp: 41000 fan: 1596 pwm: 109 pow: 160000000
gpu_vdd: 1100 gpu_clk: 1640000000 mem_clk: 167000000 temp: 41000 fan: 1618 pwm: 109 pow: 157000000
gpu_vdd: 1100 gpu_clk: 1640000000 mem_clk: 167000000 temp: 41000 fan: 1610 pwm: 109 pow: 159000000
gpu_vdd: 1100 gpu_clk: 1639000000 mem_clk: 167000000 temp: 42000 fan: 1603 pwm: 109 pow: 159000000
gpu_vdd: 1100 gpu_clk: 1638000000 mem_clk: 167000000 temp: 40000 fan: 1601 pwm: 109 pow: 162000000
gpu_vdd: 1100 gpu_clk: 1638000000 mem_clk: 167000000 temp: 42000 fan: 1603 pwm: 109 pow: 162000000
gpu_vdd: 1100 gpu_clk: 1638000000 mem_clk: 167000000 temp: 41000 fan: 1596 pwm: 109 pow: 161000000Sometimes MCLK gets stuck on 500Mhz and SCLK on 879MHz. With these clocks after some time under load my laptop makes sound notification as if power cord was disconnected and power led also switches off, then the screen looks like a TV blank screen with white noise. And I have to reboot.
Still reproducible on 5.2.2-arch1.@t.clastressaid:Same behaviour using pptables: memory either get stuck to 167MHz (level 0) or 800MHz (level 2), on 5.2 with https://aur.archlinux.org/packages/amdgpu-dkms/ which from what I understand should pull latest changes to amdgpu.
If using the classicecho "m 3 200 1050" | sudo tee /sys/class/drm/card0/device/pp_od_clk_voltageI found myself able to set an absurd memory frequency like 1400MHz which is reported to be used on my different cli tools, but it doesn't look like it does anything.(In reply to Térence Clastres from comment 10)
Same behaviour using pptables: memory either get stuck to 167MHz (level 0)
or 800MHz (level 2), on 5.2 with
https://aur.archlinux.org/packages/amdgpu-dkms/ which from what I understand
should pull latest changes to amdgpu.
If using the classicecho "m 3 200 1050" | sudo tee <br> /sys/class/drm/card0/device/pp_od_clk_voltageI found myself able to set an
absurd memory frequency like 1400MHz which is reported to be used on my
different cli tools, but it doesn't look like it does anything.
Yes, I also observe sometimes unreal freqs like 2131MHz or something. But I've noticed that when I plug the power cord of my laptop after kernel is booted in the bootloader then MCLK is set at level 500MHz and SCLK is 879MHz which is enough for all my games. But if a game is more demanding then the whole system may fail with TV static effect but it can be workarounded by sending "manual" to /sys/class/drm/card0/device/power_dpm_force_performance_level (or using corectrl https://aur.archlinux.org/packages/corectrl/) and setting level 5 in /sys/class/drm/card0/device/pp_dpm_socclk which is 847Mhz. With that setting my system is stable.
TV static is also observable when using suspend2ram on resume.@t.clastressaid:(In reply to velemas from comment 11)
(In reply to Térence Clastres from comment 10)
Same behaviour using pptables: memory either get stuck to 167MHz (level 0)
or 800MHz (level 2), on 5.2 with
https://aur.archlinux.org/packages/amdgpu-dkms/ which from what I understand
should pull latest changes to amdgpu.
If using the classicecho "m 3 200 1050" | sudo tee <br> /sys/class/drm/card0/device/pp_od_clk_voltageI found myself able to set an
absurd memory frequency like 1400MHz which is reported to be used on my
different cli tools, but it doesn't look like it does anything.
Yes, I also observe sometimes unreal freqs like 2131MHz or something. But
I've noticed that when I plug the power cord of my laptop after kernel is
booted in the bootloader then MCLK is set at level 500MHz and SCLK is 879MHz
which is enough for all my games. But if a game is more demanding then the
whole system may fail with TV static effect but it can be workarounded by
sending "manual" to
/sys/class/drm/card0/device/power_dpm_force_performance_level (or using
corectrl https://aur.archlinux.org/packages/corectrl/) and setting level 5
in /sys/class/drm/card0/device/pp_dpm_socclk which is 847Mhz. With that
setting my system is stable.
TV static is also observable when using suspend2ram on resume.
I don't know if it changes anything but I'm on a desktop system.(In reply to Térence Clastres from comment 13)
I can still reproduce with linux 5.3-rc7: Setting the memclk to anything
higher than 950MHz with a powertable makes it stuck at 800MHz.
I had the same issue (5.3-rc3).
Since i changed the value 'ucSocClockIndexHigh' in 'state 1', from 5->7 (96000->110700) i can run mclk up to 1100MHz, without problems.@t.clastressaid:(In reply to haro41 from comment 14)
(In reply to Térence Clastres from comment 13)
I can still reproduce with linux 5.3-rc7: Setting the memclk to anything
higher than 950MHz with a powertable makes it stuck at 800MHz.
I had the same issue (5.3-rc3).
Since i changed the value 'ucSocClockIndexHigh' in 'state 1', from 5->7
(96000->110700) i can run mclk up to 1100MHz, without problems.
I can't figure where ucSocClockIndexHigh is in the ppt.@t.clastressaid:(In reply to Térence Clastres from comment 15)
(In reply to haro41 from comment 14)
(In reply to Térence Clastres from comment 13)
I can still reproduce with linux 5.3-rc7: Setting the memclk to anything
higher than 950MHz with a powertable makes it stuck at 800MHz.
I had the same issue (5.3-rc3).
Since i changed the value 'ucSocClockIndexHigh' in 'state 1', from 5->7
(96000->110700) i can run mclk up to 1100MHz, without problems.
I can't figure where ucSocClockIndexHigh is in the ppt.
Found it and it works! However after reaching 1095MHz, it falls back to 800MHz but doesn't go below (167MHz or 500Mhz).(In reply to Térence Clastres from comment 16)
(In reply to Térence Clastres from comment 15)
(In reply to haro41 from comment 14)
(In reply to Térence Clastres from comment 13)
I can still reproduce with linux 5.3-rc7: Setting the memclk to anything
higher than 950MHz with a powertable makes it stuck at 800MHz.
I had the same issue (5.3-rc3).
Since i changed the value 'ucSocClockIndexHigh' in 'state 1', from 5->7
(96000->110700) i can run mclk up to 1100MHz, without problems.
I can't figure where ucSocClockIndexHigh is in the ppt.
Found it and it works! However after reaching 1095MHz, it falls back to
800MHz but doesn't go below (167MHz or 500Mhz).
I remember i adapted my UV values like this:
(cat /sys/class/drm/card0/device/pp_od_clk_voltage)
OD_SCLK:
0: 852Mhz 800mV
1: 991Mhz 850mV
2: 1084Mhz 900mV
3: 1138Mhz 910mV
4: 1200Mhz 920mV
5: 1401Mhz 940mV
6: 1536Mhz 950mV
7: 1630Mhz 1100mV
OD_MCLK:
0: 167Mhz 800mV
1: 500Mhz 800mV
2: 800Mhz 900mV
3: 1100Mhz 940mV
OD_RANGE:
SCLK: 852MHz 2400MHz
MCLK: 167MHz 1500MHz
VDDC: 800mV 1200mV
Maybe this works for you too.@t.clastressaid:(In reply to haro41 from comment 17)
(In reply to Térence Clastres from comment 16)
(In reply to Térence Clastres from comment 15)
(In reply to haro41 from comment 14)
(In reply to Térence Clastres from comment 13)
I can still reproduce with linux 5.3-rc7: Setting the memclk to anything
higher than 950MHz with a powertable makes it stuck at 800MHz.
I had the same issue (5.3-rc3).
Since i changed the value 'ucSocClockIndexHigh' in 'state 1', from 5->7
(96000->110700) i can run mclk up to 1100MHz, without problems.
I can't figure where ucSocClockIndexHigh is in the ppt.
Found it and it works! However after reaching 1095MHz, it falls back to
800MHz but doesn't go below (167MHz or 500Mhz).
I remember i adapted my UV values like this:
(cat /sys/class/drm/card0/device/pp_od_clk_voltage)
OD_SCLK:
0: 852Mhz 800mV
1: 991Mhz 850mV
2: 1084Mhz 900mV
3: 1138Mhz 910mV
4: 1200Mhz 920mV
5: 1401Mhz 940mV
6: 1536Mhz 950mV
7: 1630Mhz 1100mV
OD_MCLK:
0: 167Mhz 800mV
1: 500Mhz 800mV
2: 800Mhz 900mV
3: 1100Mhz 940mV
OD_RANGE:
SCLK: 852MHz 2400MHz
MCLK: 167MHz 1500MHz
VDDC: 800mV 1200mV
Maybe this works for you too.
Thanks, I share very similar values. I thought adjusting OD_MCLK voltages would only set core voltage floor, but I'm not sure what this mean in practice.
