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The migration is almost done, at least the rest should happen in the background. There are still a few technical difference between the old cluster and the new ones, and they are summarized in this issue. Please pay attention to the TL:DR at the end of the comment.
If I understand the driver documentation right then pp_od_clk_voltage is supposed to give out OD_SCLK, OD_MCLK, OD_VDDC_CURVE and OD_RANGE. While the first three are given, OD_RANGE is not being reported, which is necessary for UI overclock tools. Also: Are the @0mv values in the curve by design, do they have any meaning (like "default voltage" or whatever) or is that by mistake?
Is that something with Navi? On Polaris, it reports the SCLK and MCLK states, and the voltages are next to them, so the states themselves are the curve, I guess? Like, on Polaris there's no OD_VDDC_CURVE section. It looks like this:
I second that question about the difference to Polaris. Is there even a voltage+clock curve for memory for Navi (over this interface)? Or is it just not in the output?
Polaris, vega10 and older asics have a different clock management scheme compared to vega20 and newer. On the older asics there were discrete DPM states for each clock domain. On vega20 and newer, there are no longer discrete dpm states. You just have a low and a high clock limit and a voltage curve.
OK, so it now scales linearly (or in some other function) with graphics load?
Is there (supposed to be) a separate memory curve as well, or can we only set the max memory clock there, without voltage control?
Even on the older asics, the only voltage plane you can adjust is VDDC which is a dependency for both SCLK and MCLK. There were just discrete DPM states for each clock domain. E.g., if both SCLK and MCLK were in some DPM state, the higher of the two voltage settings would be used since it's the same voltage plane. On vega20 and newer, you can adjust the min and max SCLK and the max MCLK, and you can adjust the VDDC curve as it relates to SCLK.
I have a conky window that displays the output of sensors and the vddgfx bounces between 6.00 mV and 718.00 mV and power1 bounces between 4.00 W and 6.00 W with no correlation between the two while the system idles on the desktop.
It also allows me to actually edit and modify states for radeon-profile, the gpu gui overclocking tool. It doesn't allow me to edit memory though, which it does for Polaris. However, I would say that calls for a feature-request for radeon-profile if anything. Thanks for fixing this!
@agd5f Multiple sources claim this patch is active in 5.5, however it's not. Is there any reason for this not being upstreamed? Was there just not enough time for it to make it into the kernel?
Awesome! I'm applying it now to a Tk-Glitch kernel (which has worked well with the other three patches) and I'll see how it works. However I'm still having trouble figuring out how to actually overclock the thing. Using a GUI like radeon-profile, I can edit the VDDC_CURVE, which has no effect on clock speeds, or I can change the range, and when I up the range to 1820, and force a high performance level, it'll jump up to 1820, but OD_SCLK in /sys/class/drm/card0/pp_od_clk_voltage still reports 1780MHz for state 1. Which is completely different than how Polaris would act, where it had 6 or 7 states, and whichever state it was at, it would run at that clock speed (assuming temps and power draw allowed for it). And that clock speed was listed in OD_SCLK. I'll try it again with the proper voltage patch applied, but I'm not sure how else to force a clock speed for a certain state.