Commit 9b37945c authored by Daniel Schürmann's avatar Daniel Schürmann
Browse files

radv: don't lower vectorized instructions to 32bit

parent 68cf1db9
Pipeline #623113 waiting for manual action with stages
......@@ -3990,6 +3990,11 @@ lower_bit_size_callback(const nir_instr *instr, void *_)
return 0;
nir_alu_instr *alu = nir_instr_as_alu(instr);
/* If an instruction is not scalarized by this point,
* it can be emitted as packed instruction */
if (alu->dest.dest.ssa.num_components > 1)
return 0;
if (alu->dest.dest.ssa.bit_size & (8 | 16)) {
unsigned bit_size = alu->dest.dest.ssa.bit_size;
switch (alu->op) {
......@@ -4947,7 +4952,6 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
}
if (nir_lower_bit_size(stages[i].nir, lower_bit_size_callback, device)) {
NIR_PASS(_, stages[i].nir, nir_lower_alu_width, opt_vectorize_callback, device);
NIR_PASS(_, stages[i].nir, nir_opt_constant_folding);
NIR_PASS(_, stages[i].nir, nir_opt_dce);
}
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment