Commit 3353d6f3 authored by Daniel Schürmann's avatar Daniel Schürmann
Browse files

nir: Use SM5 properties to optimize shift(a@32, iand(31, b))

This is a common pattern from HLSL->SPIRV translation
and supported in HW by all current NIR backends.

vkpipeline-db results anv (SKL):
total instructions in shared programs: 6403130 -> 6402380 (-0.01%)
instructions in affected programs: 204084 -> 203334 (-0.37%)
helped: 208
HURT: 0
total cycles in shared programs: 1915629582 -> 1918198408 (0.13%)
cycles in affected programs: 1158892682 -> 1161461508 (0.22%)
helped: 107
HURT: 86
parent 70a958dd
Pipeline #21050 passed with stage
in 44 minutes and 25 seconds
......@@ -552,6 +552,11 @@ optimizations = [
(('ine', ('ineg', ('b2i', 'a@1')), -1), ('inot', a)),
(('iand', ('ineg', ('b2i', a)), 1.0), ('b2f', a)),
# SM5 32-bit shifts are defined to use the 5 least significant bits
(('ishl', 'a@32', ('iand', 31, b)), ('ishl', a, b)),
(('ishr', 'a@32', ('iand', 31, b)), ('ishr', a, b)),
(('ushr', 'a@32', ('iand', 31, b)), ('ushr', a, b)),
# Conversions
(('i2b32', ('b2i', 'a@32')), a),
(('f2i', ('ftrunc', a)), ('f2i', a)),
......
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