1. 10 Jan, 2022 7 commits
  2. 09 Jan, 2022 1 commit
    • Tapani Pälli's avatar
      iris: unref syncobjs and free r/w dependencies array for slab entries · b8f0459d
      Tapani Pälli authored and Marge Bot's avatar Marge Bot committed
      Fixes memory leak with dependencies array:
      
        ==5224== 104 (96 direct, 8 indirect) bytes in 3 blocks are definitely lost in loss record 1,954 of 2,035
        ==5224==    at 0x484178A: malloc (vg_replace_malloc.c:380)
        ==5224==    by 0x484670B: realloc (vg_replace_malloc.c:1437)
        ==5224==    by 0x14DBAB9B: update_bo_syncobjs (iris_batch.c:819)
        ==5224==    by 0x14DBADB8: update_batch_syncobjs (iris_batch.c:898)
        ==5224==    by 0x14DBB3D5: _iris_batch_flush (iris_batch.c:1031)
        ==5224==    by 0x14DB77D0: iris_transfer_map (iris_resource.c:2348)
        ==5224==    by 0x157786FD: u_transfer_helper_transfer_map (u_transfer_helper.c:243)
        ==5224==    by 0x14C479E7: tc_buffer_map (u_threaded_context.c:2252)
        ==5224==    by 0x1434F3F8: pipe_buffer_map_range (u_inlines.h:393)
        ==5224==    by 0x1435094A: _mesa_bufferobj_map_range (bufferobj.c:491)
        ==5224==    by 0x143586D9: map_buffer_range (bufferobj.c:3737)
        ==5224==    by 0x14358DA3: _mesa_MapBuffer (bufferobj.c:3947)
      
        ==5224== 240 (192 direct, 48 indirect) bytes in 6 blocks are definitely lost in loss record 1,984 of 2,035
        ==5224==    at 0x484178A: malloc (vg_replace_malloc.c:380)
        ==5224==    by 0x484670B: realloc (vg_replace_malloc.c:1437)
        ==5224==    by 0x14DBAB9B: update_bo_syncobjs (iris_batch.c:819)
        ==5224==    by 0x14DBADB8: update_batch_syncobjs (iris_batch.c:898)
        ==5224==    by 0x14DBB3D5: _iris_batch_flush (iris_batch.c:1031)
        ==5224==    by 0x14FF72CC: iris_get_query_result (iris_query.c:631)
        ==5224==    by 0x14C4396A: tc_get_query_result (u_threaded_context.c:880)
        ==5224==    by 0x1458F4F7: get_query_result (st_cb_queryobj.c:273)
        ==5224==    by 0x1458F7EB: st_WaitQuery (st_cb_queryobj.c:352)
        ==5224==    by 0x144EFF66: get_query_object (queryobj.c:742)
        ==5224==    by 0x144F01AE: _mesa_GetQueryObjectuiv (queryobj.c:811)
      
      And leak with syncobjs:
      
        ==13644== 8 bytes in 1 blocks are definitely lost in loss record 1 of 1,846
        ==13644==    at 0x484186F: malloc (vg_replace_malloc.c:381)
        ==13644==    by 0x639789B: iris_create_syncobj (iris_fence.c:69)
        ==13644==    by 0x63B213A: iris_batch_reset (iris_batch.c:512)
        ==13644==    by 0x63B3637: _iris_batch_flush (iris_batch.c:1056)
        ==13644==    by 0x65EF2BC: iris_get_query_result (iris_query.c:631)
        ==13644==    by 0x623B970: tc_get_query_result (u_threaded_context.c:880)
        ==13644==    by 0x5B874F7: get_query_result (st_cb_queryobj.c:273)
        ==13644==    by 0x5B877EB: st_WaitQuery (st_cb_queryobj.c:352)
        ==13644==    by 0x5AE7F66: get_query_object (queryobj.c:742)
        ==13644==    by 0x5AE8150: _mesa_GetQueryObjectiv (queryobj.c:801)
      
      Fixes: ce2e2296
      
       ("iris: Suballocate BO using the Gallium pb_slab mechanism")
      Signed-off-by: Tapani Pälli's avatarTapani Pälli <tapani.palli@intel.com>
      Reviewed-by: default avatarIan Romanick <ian.d.romanick@intel.com>
      Part-of: <mesa/mesa!14387>
      b8f0459d
  3. 07 Jan, 2022 32 commits
    • Christian Gmeiner's avatar
      iris/ci: update piglit fails · 9cb91010
      Christian Gmeiner authored and Marge Bot's avatar Marge Bot committed
      
      Signed-off-by: Christian Gmeiner's avatarChristian Gmeiner <christian.gmeiner@gmail.com>
      Reviewed-by: Emma Anholt's avatarEmma Anholt <emma@anholt.net>
      Part-of: <mesa/mesa!14442>
      9cb91010
    • Christian Gmeiner's avatar
      i915g/ci: update piglit fails · 4d624f18
      Christian Gmeiner authored and Marge Bot's avatar Marge Bot committed
      
      Signed-off-by: Christian Gmeiner's avatarChristian Gmeiner <christian.gmeiner@gmail.com>
      Reviewed-by: Emma Anholt's avatarEmma Anholt <emma@anholt.net>
      Part-of: <mesa/mesa!14439>
      4d624f18
    • Emma Anholt's avatar
      ci: Shrink container/rootfs sizes. · a2dbdc64
      Emma Anholt authored and Marge Bot's avatar Marge Bot committed
      
      
      Cutting the extra VK mustpass files is 315MB out of 1.5GB of the amd64
      rootfs.  pip was 10MB.  The rustup toolchains were massive (over a GB
      IIRC) on the x86 container images.
      
      Hopefully helps with #5837
      Reviewed-by: Christian Gmeiner's avatarChristian Gmeiner <christian.gmeiner@gmail.com>
      Part-of: <mesa/mesa!14460>
      a2dbdc64
    • Yiwei Zhang's avatar
      venus: subtract appended header size in vn_CreatePipelineCache · 48712b8c
      Yiwei Zhang authored and Marge Bot's avatar Marge Bot committed
      Use header->header_size to offset cache data as well in case the header
      struct extends on a newer driver but the cache data was appended with
      an old header.
      
      Fixes: 723f0bf7
      
       ("venus: initial support for module and pipelines")
      Signed-off-by: Yiwei Zhang's avatarYiwei Zhang <zzyiwei@chromium.org>
      Reviewed-by: Chia-I Wu's avatarChia-I Wu <olvaffe@gmail.com>
      Part-of: <mesa/mesa!14463>
      48712b8c
    • Danylo Piliaiev's avatar
      ir3: Assert that we cannot have enough concurrent waves for CS with barrier · 3792fbfc
      Danylo Piliaiev authored and Marge Bot's avatar Marge Bot committed
      
      
      If we have a compute shader that has a big workgroup, a barrier, and
      a branchstack which limits max_waves - this may result in a situation
      when we cannot run concurrently all waves of the workgroup, which
      would lead to a hang.
      
      Blob just explodes in such case.
      Signed-off-by: Danylo Piliaiev's avatarDanylo Piliaiev <dpiliaiev@igalia.com>
      Part-of: <!14110>
      3792fbfc
    • Danylo Piliaiev's avatar
      ir3: Be able to reduce register limit for RA when CS has barriers · 9ed4d49c
      Danylo Piliaiev authored and Marge Bot's avatar Marge Bot committed
      
      
      If barriers are used, it must be possible for all waves in the workgroup
      to execute concurrently. Thus we may have to reduce the registers limit.
      
      Fixes a hang in "Digital Combat Simulator".
      Signed-off-by: Danylo Piliaiev's avatarDanylo Piliaiev <dpiliaiev@igalia.com>
      Part-of: <!14110>
      9ed4d49c
    • He Haocheng's avatar
      zink/codegen: remove bogus print statement · 9323d2ea
      He Haocheng authored and Marge Bot's avatar Marge Bot committed
      
      Reviewed-By: Mike Blumenkrantz's avatarMike Blumenkrantz <michael.blumenkrantz@gmail.com>
      Part-of: <!14434>
      9323d2ea
    • He Haocheng's avatar
      zink/codegen: remove core_since in constructor · 37f01832
      He Haocheng authored and Marge Bot's avatar Marge Bot committed
      
      
      the variable is now automatically filled in according to registry values
      Reviewed-By: Mike Blumenkrantz's avatarMike Blumenkrantz <michael.blumenkrantz@gmail.com>
      Part-of: <!14434>
      37f01832
    • He Haocheng's avatar
      zink/codegen: support platform tags · 029e8712
      He Haocheng authored and Marge Bot's avatar Marge Bot committed
      
      
      Some extensions are locked behind certain platforms, don't include them
      if the extension is unsupported.
      Reviewed-By: Mike Blumenkrantz's avatarMike Blumenkrantz <michael.blumenkrantz@gmail.com>
      Part-of: <!14434>
      029e8712
    • Lionel Landwerlin's avatar
      anv: don't leave anv_batch fields undefined · 1d40d53e
      Lionel Landwerlin authored and Marge Bot's avatar Marge Bot committed
      
      
      Because the extend_cb vfunc is not initialized, there is a risk that
      the emission code calls into a random pointer.
      Signed-off-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Cc: mesa-stable
      Reviewed-by: Rohan Garg's avatarRohan Garg <rohan.garg@intel.com>
      Part-of: <!14418>
      1d40d53e
    • Gert Wollny's avatar
      ntt: Set the output invariant flag according to the semantics · 8685a505
      Gert Wollny authored and Marge Bot's avatar Marge Bot committed
      
      
      This is used by virglrenderer to create the correct shaders on the
      host. Fixes:
      
      dEQP-GLES31.functional.primitive_bounding_box.triangles.tessellation_set_per_primitive.vertex_tessellation_fragment.fbo
      
      when using ntt with virgl.
      Signed-off-by: Gert Wollny's avatarGert Wollny <gert.wollny@collabora.com>
      Reviewed-by: Emma Anholt's avatarEmma Anholt <emma@anholt.net>
      Part-of: <!14423>
      8685a505
    • Gert Wollny's avatar
      nir_lower_io: propagate the "invariant" flag to outputs · 6f348d9c
      Gert Wollny authored and Marge Bot's avatar Marge Bot committed
      
      
      Ultimately this is consumed by nir-to-tgsi and needed by virglrenderer
      to correctly declare output variables.
      Signed-off-by: Gert Wollny's avatarGert Wollny <gert.wollny@collabora.com>
      Reviewed-by: Emma Anholt's avatarEmma Anholt <emma@anholt.net>
      Part-of: <!14423>
      6f348d9c
    • Gert Wollny's avatar
      util/primconvert: map only index buffer part that is needed · 5bfe2927
      Gert Wollny authored and Marge Bot's avatar Marge Bot committed
      By putting vertex store and indices all in one buffer the larger part
      of the shared buffer might actually only be vertex data we are not
      interested in. Hence only map the part of the buffer that contains the
      index data for the currently active draw command.
      
      This helps drivers where a mapping operation is expensive, like e.g. virgl.
      
      v2: - add comment about ranged buffer mapping (Pierre-Eric)
          - keep passing direct_draws[i].start to direct_draw_func, it looks
            like the "start" parameter is properly set in
            util_prim_restart_convert_to_direct
      
      v3: Fix ws error (Mike)
      
      Related: #5825
      
      Fixes: f9d12bf5
      
      
         vbo/dlist: use a single buffer object
      Signed-off-by: Gert Wollny's avatarGert Wollny <gert.wollny@collabora.com>
      Reviewed-By: Mike Blumenkrantz's avatarMike Blumenkrantz <michael.blumenkrantz@gmail.com>
      Part-of: <!14423>
      5bfe2927
    • Christian Gmeiner's avatar
      etnaviv/ci: update piglit fails · 86b19db4
      Christian Gmeiner authored and Marge Bot's avatar Marge Bot committed
      
      Signed-off-by: Christian Gmeiner's avatarChristian Gmeiner <christian.gmeiner@gmail.com>
      Part-of: <!14441>
      86b19db4
    • Rhys Perry's avatar
      radv: increase maxTaskOutputCount to 65535 · 1756930a
      Rhys Perry authored and Marge Bot's avatar Marge Bot committed
      
      
      This is the minimum required by the spec.
      
      Fixes dEQP-VK.api.info.vulkan1p2_limits_validation.nv_mesh_shader
      Signed-off-by: Rhys Perry's avatarRhys Perry <pendingchaos02@gmail.com>
      Reviewed-by: Samuel Pitoiset's avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
      Part-of: <!14446>
      1756930a
    • Connor Abbott's avatar
      ir3: Use (ss) for instructions writing shared regs · cb451205
      Connor Abbott authored and Marge Bot's avatar Marge Bot committed
      The blob uses *both* nops and (ss). It turns out that in some rare cases
      the hardware does take more than 6 cycles, at least for movmsk, but
      adding nops is unnecessary. I believe the extra nops are only there due
      to the immaturity of the blob's implementation of subgroup ops, so we
      don't have to copy them - just handle shared reg producers the same as
      SFU instructions.
      
      Part-of: <!14246>
      cb451205
    • Connor Abbott's avatar
      ir3/postsched: Rename tex/sfu to sy/ss · d45678ca
      Connor Abbott authored and Marge Bot's avatar Marge Bot committed
      Analogous to the previous commit.
      
      Part-of: <!14246>
      d45678ca
    • Connor Abbott's avatar
      ir3/sched: Rename tex/sfu to sy/ss · e6b35d60
      Connor Abbott authored and Marge Bot's avatar Marge Bot committed
      This now covers e.g. cat6 instructions as well, and ss will cover
      instructions writing shared regs as well. This is split out from the
      previous change to avoid too much churn and shouldn't cause any
      functional changes.
      
      Part-of: <!14246>
      e6b35d60
    • Connor Abbott's avatar
      ir3: Use new (sy)/(ss) stall helpers in the compiler · 0cc4aca3
      Connor Abbott authored and Marge Bot's avatar Marge Bot committed
      This fixes a few bad assumptions in the pre-RA and post-RA scheduler,
      for example that (sy) is only for texture instructions and (ss) is only
      for SFU instructions and (sy) and (ss) producers will always take the
      same number of cycles. This means we now start doing latency hiding for
      cat6 instructions like ldib and ldc. It also should make us hide latency
      more aggressively, since the number used for (sy) stall cycles was way
      lower than the real numbers for everything except ldc. Finally it
      unifies the various places (ss) soft nops were calculated.
      
      selected shader-db results:
      
      total nops in shared programs: 345278 -> 358959 (3.96%)
      nops in affected programs: 215622 -> 229303 (6.34%)
      helped: 690
      HURT: 2430
      helped stats (abs) min: 1 max: 125 x̄: 11.40 x̃: 5
      helped stats (rel) min: 0.53% max: 100.00% x̄: 24.19% x̃: 18.52%
      HURT stats (abs)   min: 1 max: 501 x̄: 8.87 x̃: 5
      HURT stats (rel)   min: 0.00% max: 9900.00% x̄: 52.36% x̃: 14.29%
      95% mean confidence interval for nops value: 3.78 4.99
      95% mean confidence interval for nops %-change: 28.21% 42.66%
      Nops are HURT.
      
      total mov in shared programs: 75049 -> 74110 (-1.25%)
      mov in affected programs: 15754 -> 14815 (-5.96%)
      helped: 566
      HURT: 455
      helped stats (abs) min: 1 max: 36 x̄: 4.52 x̃: 3
      helped stats (rel) min: 0.83% max: 100.00% x̄: 35.85% x̃: 30.00%
      HURT stats (abs)   min: 1 max: 35 x̄: 3.55 x̃: 3
      HURT stats (rel)   min: 0.00% max: 1100.00% x̄: 63.60% x̃: 25.00%
      95% mean confidence interval for mov value: -1.25 -0.58
      95% mean confidence interval for mov %-change: 2.92% 14.02%
      Inconclusive result (value mean confidence interval and %-change mean
      confidence interval disagree).
      
      total last-baryf in shared programs: 80468 -> 67670 (-15.90%)
      last-baryf in affected programs: 63676 -> 50878 (-20.10%)
      helped: 309
      HURT: 147
      helped stats (abs) min: 1 max: 260 x̄: 49.20 x̃: 24
      helped stats (rel) min: 0.60% max: 98.81% x̄: 37.92% x̃: 40.91%
      HURT stats (abs)   min: 1 max: 115 x̄: 16.35 x̃: 12
      HURT stats (rel)   min: 0.96% max: 1933.33% x̄: 45.55% x̃: 7.89%
      95% mean confidence interval for last-baryf value: -33.03 -23.10
      95% mean confidence interval for last-baryf %-change: -21.52% -0.50%
      Last-baryf are helped.
      
      total sstall in shared programs: 133997 -> 126398 (-5.67%)
      sstall in affected programs: 86866 -> 79267 (-8.75%)
      helped: 1893
      HURT: 598
      helped stats (abs) min: 1 max: 77 x̄: 6.06 x̃: 4
      helped stats (rel) min: 0.71% max: 100.00% x̄: 32.82% x̃: 16.67%
      HURT stats (abs)   min: 1 max: 65 x̄: 6.47 x̃: 6
      HURT stats (rel)   min: 0.00% max: 900.00% x̄: 65.51% x̃: 25.00%
      95% mean confidence interval for sstall value: -3.39 -2.71
      95% mean confidence interval for sstall %-change: -12.19% -6.24%
      Sstall are helped.
      
      total systall in shared programs: 350304 -> 288234 (-17.72%)
      systall in affected programs: 234855 -> 172785 (-26.43%)
      helped: 1456
      HURT: 260
      helped stats (abs) min: 1 max: 574 x̄: 46.42 x̃: 27
      helped stats (rel) min: 0.19% max: 100.00% x̄: 39.43% x̃: 36.06%
      HURT stats (abs)   min: 1 max: 757 x̄: 21.20 x̃: 8
      HURT stats (rel)   min: 0.00% max: 180.95% x̄: 24.82% x̃: 12.50%
      95% mean confidence interval for systall value: -39.31 -33.03
      95% mean confidence interval for systall %-change: -31.49% -27.90%
      Systall are helped.
      
      total waves in shared programs: 236732 -> 235142 (-0.67%)
      waves in affected programs: 6142 -> 4552 (-25.89%)
      helped: 535
      HURT: 17
      helped stats (abs) min: 2 max: 8 x̄: 3.08 x̃: 2
      helped stats (rel) min: 12.50% max: 75.00% x̄: 28.78% x̃: 25.00%
      HURT stats (abs)   min: 2 max: 6 x̄: 3.53 x̃: 4
      HURT stats (rel)   min: 16.67% max: 75.00% x̄: 37.35% x̃: 33.33%
      95% mean confidence interval for waves value: -3.04 -2.72
      95% mean confidence interval for waves %-change: -28.10% -25.39%
      Waves are helped.
      
      Part-of: <!14246>
      0cc4aca3
    • Connor Abbott's avatar
      ir3: Introduce systall metric and new helper functions · 7e60978d
      Connor Abbott authored and Marge Bot's avatar Marge Bot committed
      Add new centralized functions which will replace the various places we
      hardcode 10 for the number of (ss) nops, add numbers for soft (sy) nops
      based on similar computerator experiments with ldc, sam, and ldib (the
      most common (sy) producers), and add a "systall" metric which is
      analogous to sstall. This also fixes some cases where we'd erroniously
      count ldl* as (sy) producers instead of (ss) producers when calculating
      sstall.
      
      This only switches over the metric reporting to the new functions, so
      there is no behavior change. The following commit will switch over
      the rest of the compiler.
      
      While we're at it, remove max_sun as it's never set.
      
      Part-of: <mesa/mesa!14246>
      7e60978d
    • Connor Abbott's avatar
      ir3: Bump type mismatch penalty to 3 · 603791bd
      Connor Abbott authored and Marge Bot's avatar Marge Bot committed
      After some experimentation with computerator, it seems on a618 that
      writing a full register and then reading half of it as a half register
      requires a delay of 6, the same as the delay for cat5/cat6 sources. The
      other direction only has a delay of 5, but just bump it unconditionally
      out of an abundance of caution.
      
      Fixes: 890de1a4 ("ir3/delay: Fix full->half and half->full delay")
      Part-of: <mesa/mesa!14246>
      603791bd
    • Connor Abbott's avatar
      ir3/ra: Fix logic bug in compress_regs_left · d371d807
      Connor Abbott authored and Marge Bot's avatar Marge Bot committed
      If we're allocating a source then we force is_killed to false, not to
      true. Fixes a regression in
      dEQP-GLES31.functional.synchronization.in_invocation.image_atomic_write_read
      later.
      
      Fixes: 0ffcb19b ("ir3: Rewrite register allocation")
      Part-of: <!14246>
      d371d807
    • Tomeu Vizoso's avatar
      anv/tests: Free BO cache and device mutex · c9adcb60
      Tomeu Vizoso authored and Marge Bot's avatar Marge Bot committed
      Was getting ASAN errors in CI when trying to add ANV to the
      debian-testing job:
      
      ==10993==ERROR: LeakSanitizer: detected memory leaks
      
      Direct leak of 4194304 byte(s) in 64 object(s) allocated from:
          #0 0x7f763c1bda3c in __interceptor_posix_memalign ../../../../src/libsanitizer/asan/asan_malloc_linux.cpp:226
          #1 0x55f43d28627f in os_malloc_aligned ../src/util/os_memory_aligned.h:58
          #2 0x55f43d28627f in _util_sparse_array_node_alloc ../src/util/sparse_array.c:107
          #3 0x55f43d28627f in util_sparse_array_get ../src/util/sparse_array.c:143
          #4 0x55f43d1fdaba in anv_device_lookup_bo ../src/intel/vulkan/anv_private.h:1335
          #5 0x55f43d1fdaba in anv_device_import_bo_from_host_ptr ../src/intel/vulkan/anv_allocator.c:1843
          #6 0x55f43d1ff571 in anv_block_pool_expand_range ../src/intel/vulkan/anv_allocator.c:534
          #7 0x55f43d1ffcb5 in anv_block_pool_init ../src/intel/vulkan/anv_allocator.c:417
          #8 0x55f43d18f082 in run_test ../src/intel/vulkan/tests/block_pool_no_free.c:123
          #9 0x55f43d1862b6 in main ../src/intel/vulkan/tests/block_pool_no_free.c:152
          #10
      
       0x7f763b942d09 in __libc_start_main ../csu/libc-start.c:308
      Signed-off-by: Tomeu Vizoso's avatarTomeu Vizoso <tomeu.vizoso@collabora.com>
      Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Part-of: <!14121>
      c9adcb60
    • Tomeu Vizoso's avatar
      anv/ci: Test with deqp-vk on Tiger Lake · 8a7659a7
      Tomeu Vizoso authored and Marge Bot's avatar Marge Bot committed
      
      
      Run half of the CTS in 10 Volteer Chromebook devices.
      Signed-off-by: Tomeu Vizoso's avatarTomeu Vizoso <tomeu.vizoso@collabora.com>
      Reviewed-by: Emma Anholt's avatarEmma Anholt <emma@anholt.net>
      Part-of: <!14121>
      8a7659a7
    • Jesse Natalie's avatar
      shader_info: tess.spacing needs to be unsigned · ef27036b
      Jesse Natalie authored and Marge Bot's avatar Marge Bot committed
      
      
      Otherwise MSVC will treat the bit-packed enum values as signed.
      Reviewed-by: default avatarMarek Olšák <marek.olsak@amd.com>
      Part-of: <mesa/mesa!14402>
      ef27036b
    • Philipp Zabel's avatar
      etnaviv: fix emit_if in case the else block ends in a jump · 1b808f1d
      Philipp Zabel authored and Marge Bot's avatar Marge Bot committed
      
      
      Fixes piglit test shaders@ssa@fs-if-def-else-break.
      Signed-off-by: Philipp Zabel's avatarPhilipp Zabel <p.zabel@pengutronix.de>
      Reviewed-by: Lucas Stach's avatarLucas Stach <l.stach@pengutronix.de>
      Reviewed-by: Christian Gmeiner's avatarChristian Gmeiner <christian.gmeiner@gmail.com>
      Part-of: <mesa/mesa!12892>
      1b808f1d
    • Rohan Garg's avatar
      intel/fs: OpImageQueryLod does not support arrayed images as an operand · af131199
      Rohan Garg authored and Marge Bot's avatar Marge Bot committed
      When we lower SPIR-V to NIR for textures in vtn_handle_texture, we only
      bump the number of coordinate components when the op is not a lod query.
      Update the assert to take this into account.
      
      This fixes:
        - dEQP-VK.robustness.robustness2.bind.template.r32f.dontunroll.nonvolatile.sampled_image.no_fmt_qual.null_descriptor.samples_1.cube_array.frag
        - dEQP-VK.robustness.robustness2.bind.template.r32f.unroll.nonvolatile.sampled_image.no_fmt_qual.null_descriptor.samples_1.cube_array.frag
        - dEQP-VK.robustness.robustness2.bind.template.r32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.null_descriptor.samples_1.cube_array.frag
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      Fixes: 231337a1
      
       ("intel/fs/xehp: Assert that the compiler is sending all 3 coords for cubemaps.")
      Signed-off-by: Rohan Garg's avatarRohan Garg <rohan.garg@intel.com>
      Reviewed-by: Francisco Jerez's avatarFrancisco Jerez <currojerez@riseup.net>
      Reviewed-by: Sagar Ghuge's avatarSagar Ghuge <sagar.ghuge@intel.com>
      Reviewed-by: Jason Ekstrand's avatarJason Ekstrand <jason@jlekstrand.net>
      Part-of: <mesa/mesa!13925>
      af131199
    • Emma Anholt's avatar
      nir_to_tgsi: Enable fdot_replicates flag. · 558a6006
      Emma Anholt authored and Marge Bot's avatar Marge Bot committed
      
      
      That's how the TGSI math opcodes work.
      
      This lets lower_vec_to_regs coalesce the DP output into the .yzw channels,
      giving an impressive shader-db win on softpipe:
      
      total instructions in shared programs: 2929840 -> 2794036 (-4.64%)
      instructions in affected programs: 1651438 -> 1515634 (-8.22%)
      total temps in shared programs: 372730 -> 332744 (-10.73%)
      temps in affected programs: 118151 -> 78165 (-33.84%)
      
      and a minor one on r300:
      
      total instructions in shared programs: 51238 -> 51149 (-0.17%)
      instructions in affected programs: 2621 -> 2532 (-3.40%)
      total vinst in shared programs: 15655 -> 15618 (-0.24%)
      vinst in affected programs: 468 -> 431 (-7.91%)
      total temps in shared programs: 9838 -> 9828 (-0.10%)
      temps in affected programs: 59 -> 49 (-16.95%)
      
      and a bigger one on i915g:
      total instructions in shared programs: 398064 -> 395901 (-0.54%)
      instructions in affected programs: 29271 -> 27108 (-7.39%)
      total tex_indirect in shared programs: 12261 -> 12233 (-0.23%)
      tex_indirect in affected programs: 98 -> 70 (-28.57%)
      LOST:   0
      GAINED: 5
      
      The r300 change is less impressive because it does some backend copy-prop,
      but also because intermediate storage of DPs now takes a vec4 instead of a
      scalar.
      Reviewed-by: Jason Ekstrand's avatarJason Ekstrand <jason@jlekstrand.net>
      Part-of: <mesa/mesa!14200>
      558a6006
    • Christian Gmeiner's avatar
      panfrost/ci: update piglit fails · 85d7d520
      Christian Gmeiner authored and Marge Bot's avatar Marge Bot committed
      
      Signed-off-by: Christian Gmeiner's avatarChristian Gmeiner <christian.gmeiner@gmail.com>
      Part-of: <mesa/mesa!14428>
      85d7d520
    • Francisco Jerez's avatar
      intel/dev: Implement DG2 restrictions requiring additional DSSes to be disabled. · 054eb9f3
      Francisco Jerez authored and Marge Bot's avatar Marge Bot committed
      
      
      Note that this causes a geometry slice to be disabled if any DSS is
      fused off within that slice, which may seem stricter than the BSpec
      quotation implies, but testing shows that pixel pipes with any faulted
      DSS don't work at all, and that using a slice with any faulted pixel
      pipe leads to serious graphics corruption.
      
      It would be better to query this geometry topology information from
      the hardware instead of trying to reconstruct it here, but the kernel
      interface for that is not available yet.
      Reviewed-by: Caio Oliveira's avatarCaio Oliveira <caio.oliveira@intel.com>
      Part-of: <mesa/mesa!14436>
      054eb9f3
    • Francisco Jerez's avatar
      e48c29ac
    • Francisco Jerez's avatar
      intel/dev: Fix size of device info num_subslices array. · f3274e94
      Francisco Jerez authored and Marge Bot's avatar Marge Bot committed
      
      Reviewed-by: Caio Oliveira's avatarCaio Oliveira <caio.oliveira@intel.com>
      Part-of: <mesa/mesa!14436>
      f3274e94