Commit f1f65e5b authored by Nanley Chery's avatar Nanley Chery Committed by Marge Bot
Browse files

intel/isl: Allow creating MCS in Tile4 memory



This enables MCS support on XeHP, now that MCS can be created with a
tiling supported by that platform.

Reviewed-by: Tapani Pälli's avatarTapani Pälli <tapani.palli@intel.com>
Acked-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
Part-of: <mesa/mesa!14464>
parent f960e398
...@@ -828,8 +828,6 @@ isl_choose_image_alignment_el(const struct isl_device *dev, ...@@ -828,8 +828,6 @@ isl_choose_image_alignment_el(const struct isl_device *dev,
{ {
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
if (fmtl->txc == ISL_TXC_MCS) { if (fmtl->txc == ISL_TXC_MCS) {
assert(tiling == ISL_TILING_Y0);
/* /*
* IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)": * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
* *
...@@ -2084,7 +2082,7 @@ isl_surf_get_mcs_surf(const struct isl_device *dev, ...@@ -2084,7 +2082,7 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
.array_len = surf->logical_level0_px.array_len, .array_len = surf->logical_level0_px.array_len,
.samples = 1, /* MCS surfaces are really single-sampled */ .samples = 1, /* MCS surfaces are really single-sampled */
.usage = ISL_SURF_USAGE_MCS_BIT, .usage = ISL_SURF_USAGE_MCS_BIT,
.tiling_flags = ISL_TILING_Y0_BIT); .tiling_flags = ISL_TILING_ANY_MASK);
} }
bool bool
...@@ -2147,7 +2145,6 @@ isl_surf_supports_ccs(const struct isl_device *dev, ...@@ -2147,7 +2145,6 @@ isl_surf_supports_ccs(const struct isl_device *dev,
return false; return false;
assert(mcs_surf->usage & ISL_SURF_USAGE_MCS_BIT); assert(mcs_surf->usage & ISL_SURF_USAGE_MCS_BIT);
assert(isl_tiling_is_any_y(mcs_surf->tiling));
assert(isl_format_is_mcs(mcs_surf->format)); assert(isl_format_is_mcs(mcs_surf->format));
} else { } else {
/* Single-sampled color can't have MCS or HiZ */ /* Single-sampled color can't have MCS or HiZ */
......
...@@ -54,6 +54,13 @@ isl_gfx125_filter_tiling(const struct isl_device *dev, ...@@ -54,6 +54,13 @@ isl_gfx125_filter_tiling(const struct isl_device *dev,
if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT)
*flags &= ~ISL_TILING_64_BIT; *flags &= ~ISL_TILING_64_BIT;
/* From RENDER_SURFACE_STATE::AuxiliarySurfaceMode,
*
* MCS tiling format is always Tile4
*/
if (info->usage & ISL_SURF_USAGE_MCS_BIT)
*flags &= ISL_TILING_4_BIT;
/* From RENDER_SURFACE_STATE::TileMode, /* From RENDER_SURFACE_STATE::TileMode,
* *
* TILEMODE_XMAJOR is only allowed if Surface Type is SURFTYPE_2D. * TILEMODE_XMAJOR is only allowed if Surface Type is SURFTYPE_2D.
......
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