- 09 Sep, 2019 5 commits
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Connor Abbott authored
The entire point of schedule_first is that the node has to be scheduled as soon as possible without any moves because it doesn't produce a proper floating-point value, or its value changes depending on where you read it. We were still introducing a move for preexp2 in some cases though, even if it got scheduled as soon as possible, which broke some exp() tests. Fix that. Reviewed-by:
Vasily Khoruzhick <anarsoul@gmail.com> Tested-by:
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Connor Abbott authored
The whole point of schedule_first nodes is that they need to be scheduled as soon as possible, so if a schedule_first node is the successor in a fake dependency that prevents it from being scheduled after its parent, that can cause problems. We need to add these fake dependencies to the parent as well, and we need to guarantee that the pre-RA scheduler puts schedule_first nodes right before their parents in order to prevent this from adding cycles to the dependency graph. Reviewed-by:
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Connor Abbott authored
The idea was to make sure schedule_first nodes were always first in the ready list. I made sure they were inserted first, but not that other nodes wouldn't later be scheduled ahead of them. Fixes spec@glsl-1.10@execution@built-in-functions@vs-exp-float and probably others. Reviewed-by:
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Connor Abbott authored
The point of the function is to avoid creating a complex move which is used by certain slots in the next instruction, but unscheduled successors will never be in the next instruction. Found while debugging a crash that the previous commit fixed. Reviewed-by:
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Connor Abbott authored
The scheduler assumes that load nodes are always duplicated so that they can always be scheduled eventually and therefore they never need to be spilled. But some lowerings were running after the pre-RA scheduler, whereas duplication has to happen before then since it's needed for the scheduler to do a better job reducing register pressure. This meant that lowerings were introducing multiple uses of a load instruction, which broke the scheduler's expectation and resulted in infinite loops in situations where the only nodes available to spill were load nodes. Spilling load nodes would be silly, so we want to fix the lowerings rather than the scheduler. Just do all lowerings before the pre-RA scheduler, which also helps with reducing pressure since the scheduler can more accurately compute the pressure. Fixes lima/mesa#104 . Reviewed-by:
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- 08 Sep, 2019 13 commits
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maurossi authoredChange needed to fix the following building error: In file included from external/mesa/src/intel/vulkan/anv_device.c:43: external/mesa/src/util/xmlpool.h:115:10: fatal error: 'xmlpool/options.h' file not found ^~~~~~~~~~~~~~~~~~~ 1 error generated. Fixes: 4dcb1fff ("anv: add support for driconf") Signed-off-by:
Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
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Boris Brezillon authored
So we can move all the BO logic into this file instead of having it spread over pan_resource.c, pan_drm.c and pan_bo_cache.c. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> -
Boris Brezillon authored
The last users have been converted to use plain BOs. Let's get rid of this abstraction. We can always consider adding it back if we need it at some point. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> -
Boris Brezillon authored
Some fields in panfrost_context are unused (probably leftovers from previous refactor). Let's get rid of them. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> -
Boris Brezillon authored
ctx->{scratchpad,tiler_heap,tiler_dummy} are allocated using panfrost_drm_allocate_slab() but they never any of the SLAB-based allocation logic. Let's convert those fields to plain BOs. Signed-off-by:Alyssa Rosenzweig <alyssa@rosenzweig.io> -
Boris Brezillon authored
Right now, the transient memory allocator implements its own BO caching mechanism, which is not really needed since we already have a generic BO cache. Let's simplify things a bit. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io> -
Boris Brezillon authored
The context can be retrieved from batch->ctx. Signed-off-by:
Daniel Stone <daniels@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> -
Boris Brezillon authored
Given the function name it makes more sense to pass it a job batch directly. Signed-off-by:
Daniel Stone <daniels@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> -
Boris Brezillon authored
What we currently call a job is actually a batch containing several jobs all attached to a rendering operation targeting a specific FBO. Let's rename structs, functions, variables and fields to reflect this fact. Suggested-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> -
This commit follow OES_EGL_sync to universially enable use of EGL sync objects with desktop OpenGL contexts. Reviewed-by:
Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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Reviewed-by:
Daniel Stone <daniels@collabora.com>
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As added by upstream GL registry changes Reviewed-by:
Daniel Stone <daniels@collabora.com>
Reviewed-by: -
Adds GL_MESA_EGL_sync as defined in upstream OpenGL registry Reviewed-by:
Daniel Stone <daniels@collabora.com>
Reviewed-by:
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- 07 Sep, 2019 2 commits
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Tapani Pälli authoredFixes Android build errors observed in Intel CI. Fixes: f9f7cbc1 "util: android logging support" Signed-off-by:
Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
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Kenneth Graunke authored
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- 06 Sep, 2019 20 commits
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Faith Ekstrand authoredThe dead_cf pass calls into the CF manipulation helpers which attempt to keep NIR's SSA form sane. However, when the only break is removed from a loop, dominance gets messed up anyway because the CF SSA clean-up code only looks at phis and doesn't consider the case of code becoming unreachable. One solution to this would be to put the loop into LCSSA form before we modify any of its contents. Another (and the approach taken by this pass) is to just run the repair_ssa pass afterwards because the CF manipulation helpers are smart enough to keep all the use/def stuff sane; they just don't always preserve dominance properties. While we're here, we clean up some bogus indentation. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111405 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111069 Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
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Faith Ekstrand authored
Cc: mesa-stable@lists.freedesktop.org Reviewed-by: -
Faith Ekstrand authored
NIR currently assumes that unreachable blocks are trivially dominated by everything. However, when considering well-formed SSA, there is no path from any block to an unreachable block. Therefore, we can break any use-def chains where the use is in an unreachable block. This removes any dependencies on code created by uses in unreachable blocks and lets DCE do a better job of cleaning it up. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: -
Faith Ekstrand authored
Cc: mesa-stable@lists.freedesktop.org Reviewed-by: -
Faith Ekstrand authored
Cc: mesa-stable@lists.freedesktop.org Reviewed-by: -
Faith Ekstrand authored
We already bail and don't split the vars but we were passing a NULL to _mesa_hash_table_search which is not allowed. Fixes: f1cb3348 "nir/split_vars: Properly bail in the presence of ..." Reviewed-by:
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In the case where the stencil clear is nicely aligned, we can clear stencil much more efficiently by mapping it as a wide format (say RGBA32_UINT) and blasting out the stencil clear value with a repclear. On Unigine Heaven, this makes one stencil clear go from non-trivial to unnoticeable when looking at per-draw timings. In order for this change to work properly, ANV needs to do a bit more flushing around depth and stencil clears. i965 and iris already have the cache tracking logic to handle this so no changes are required there. Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: 
Lionel Landwerlin <lionel.g.landwerlin@intel.com> -
Faith Ekstrand authored
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Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> -
Faith Ekstrand authored
This isn't known to fix any current bugs but it does prevent a regression in a subsequent commit. Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> -
Faith Ekstrand authored
Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> -
Faith Ekstrand authored
Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> -
Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com>
Fixes: 02bc4aabb48 ('nir/lower_io_to_vector: allow FS outputs to be vectorized')
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> -
Eric Engestrom authored
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110765 Fixes: 4689e98f ("vulkan/wsi: Set X11 minImageCount to 3.") Signed-off-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Tested-by:
Eero Tamminen <eero.t.tamminen@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> -
Eric Engestrom authored
Cc: mesa-stable@lists.freedesktop.org Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> -
Eric Engestrom authored
Fixes: 3844ed8d ("radv: Add adaptive_sync driconfig option and enable it by default.") Fixes: e260493f ("radeonsi: Enable adaptive_sync by default for radeon") Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> -
Eric Engestrom authored
Cc: mesa-stable@lists.freedesktop.org Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> -
Eric Engestrom authored
Cc: mesa-stable@lists.freedesktop.org Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> -
Eric Engestrom authored
No option is supported yet, this is just the boilerplate. Cc: mesa-stable@lists.freedesktop.org Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> -
Eric Engestrom authored
Suggested-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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