Commit 7129f33a authored by Alyssa Rosenzweig's avatar Alyssa Rosenzweig 💜
Browse files

[WIP] ld_var



WIP because this needs more r/e, and it's too late in the day for me to
do nontrivial r/e, so punting.
Signed-off-by: Alyssa Rosenzweig's avatarAlyssa Rosenzweig <alyssa@collabora.com>
parent 05d82bb3
Pipeline #370691 waiting for manual action with stages
......@@ -8301,4 +8301,64 @@
<mod name="abs1" start="15" size="1" opt="abs"/>
</ins>
<ins name="+LD_VAR_IMM_F32" staging="w=format" message="varying" pseudo="true">
<src start="0"/>
<src start="3"/>
<immediate name="index" start="3" size="5"/>
<mod name="vecsize" start="8" size="2">
<opt>none</opt>
<opt>v2</opt>
<opt>v3</opt>
<opt>v4</opt>
</mod>
<mod name="update" size="2">
<opt>store</opt>
<opt>retrieve</opt>
<opt>conditional</opt>
<opt>clobber</opt>
</mod>
<mod name="register_format" size="2">
<opt>f32</opt>
<opt>f16</opt>
<opt>auto</opt>
</mod>
<mod name="sample" size="3">
<opt>center</opt>
<opt>centroid</opt>
<opt>sample</opt>
<opt>explicit</opt>
<opt>none</opt>
</mod>
</ins>
<ins name="+LD_VAR_IMM_F16" staging="w=format" message="varying" pseudo="true">
<src start="0"/>
<src start="3"/>
<immediate name="index" start="3" size="5"/>
<mod name="vecsize" start="8" size="2">
<opt>none</opt>
<opt>v2</opt>
<opt>v3</opt>
<opt>v4</opt>
</mod>
<mod name="update" size="2">
<opt>store</opt>
<opt>retrieve</opt>
<opt>conditional</opt>
<opt>clobber</opt>
</mod>
<mod name="register_format" size="2">
<opt>f32</opt>
<opt>f16</opt>
<opt>auto</opt>
</mod>
<mod name="sample" size="3">
<opt>center</opt>
<opt>centroid</opt>
<opt>sample</opt>
<opt>explicit</opt>
<opt>none</opt>
</mod>
</ins>
</bifrost>
......@@ -106,3 +106,7 @@ c0 01 00 00 00 c4 10 51 IADD_IMM.i32.reconverge r4, 0x0, #0x1
04 00 00 00 00 c7 91 08 MOV.i32.wait0 r7, r4
42 00 00 38 08 44 61 00 STORE.i128.slot0 @r4:r5:r6:r7, `r2, offset:0
41 f8 ff ff 07 c0 1f 50 BRANCHZ.reconverge `r1, offset:-8
3d 00 00 33 84 80 5d 00 LD_VAR_IMM_F16.v4.f16.slot0 @r0:r1, r61, r0, index:0x0
3d 00 00 32 88 80 5c 00 LD_VAR_IMM_F32.v4.f32.slot0 @r0:r1:r2:r3, r61, r0, index:0x0
3d 00 00 12 84 80 5c 00 LD_VAR_IMM_F32.v2.f32.slot0 @r0:r1, r61, r0, index:0x0
3d 00 00 33 84 80 5d 00 LD_VAR_IMM_F16.v4.f16.slot0 @r0:r1, r61, r0, index:0x0
......@@ -169,5 +169,13 @@ main(int argc, const char **argv)
CASE(I, 0x007dbc0200ead03c);
}
{
bi_instr *I = bi_ld_var_imm_f32_to(b, bi_register(0), bi_register(61),
bi_register(0), BI_REGISTER_FORMAT_F32,
BI_SAMPLE_CENTER, BI_UPDATE_STORE,
BI_VECSIZE_V4, 0);
CASE(I, 0x005c80883200003d);
}
TEST_END(nr_pass, nr_fail);
}
......@@ -77,6 +77,10 @@ va_lower_isel(bi_instr *I)
I->cmpf = BI_CMPF_EQ;
break;
case BI_OPCODE_LD_VAR_IMM:
I->op = BI_OPCODE_LD_VAR_IMM_F32;
break;
default:
break;
}
......
......@@ -73,8 +73,6 @@ SKIP = set([
"TEX",
"TODO.VAR_TEX",
"BRANCHZI",
"LD_VAR_IMM_F32",
"LD_VAR_IMM_F16",
"ST_IMAGE",
"NOT.i32",
])
......
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