From b0ce597bbf223cfe07524b86eba4f9a057aa1ac6 Mon Sep 17 00:00:00 2001
From: Anthony Koo <anthony.koo@amd.com>
Date: Sat, 13 Apr 2024 23:50:03 -0400
Subject: [PATCH] drm/amd/display: [FW Promotion] Release 0.0.214.0
- Adjust the dmub_fw_boot_options reserved bits to be correct
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Anthony Koo <anthony.koo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index bb4aed3293939..7a0574e6c129b 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -655,7 +655,7 @@ union dmub_fw_boot_options {
uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/
uint32_t ips_disable: 3; /* options to disable ips support*/
uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */
- uint32_t reserved : 9; /**< reserved */
+ uint32_t reserved : 8; /**< reserved */
} bits; /**< boot bits */
uint32_t all; /**< 32-bit access to bits */
};
--
GitLab