diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index a9bf9c784b7c578cd747c1d84151477fb3201cea..b64f810189ff366fc2d6d3051722c35f42eaf8d9 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -200,6 +200,8 @@ struct xe_device { const char *graphics_name; /** @media_name: media IP name */ const char *media_name; + /** @tile_mmio_ext_size: size of MMIO extension space, per-tile */ + u32 tile_mmio_ext_size; /** @graphics_verx100: graphics IP version */ u32 graphics_verx100; /** @media_verx100: media IP version */ @@ -245,6 +247,8 @@ struct xe_device { u8 has_range_tlb_invalidation:1; /** @bypass_mtcfg: Bypass Multi-Tile configuration from MTCFG register */ u8 bypass_mtcfg:1; + /** @supports_mmio_ext: supports MMIO extension/s */ + u8 supports_mmio_ext:1; } info; /** @irq: device interrupt state */ diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index f8e813e174580f7f3fd12e76a24e94f8ad1993a4..8161982796dd2ef6ae9d934d158b6e031c5ef9ba 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -57,6 +57,7 @@ struct xe_device_desc { u8 is_dgfx:1; u8 has_llc:1; u8 bypass_mtcfg:1; + u8 supports_mmio_ext:1; }; #define PLATFORM(x) \ @@ -555,6 +556,8 @@ static int xe_info_init(struct xe_device *xe, xe->info.media_name = media_desc ? media_desc->name : "none"; xe->info.has_llc = desc->has_llc; xe->info.bypass_mtcfg = desc->bypass_mtcfg; + xe->info.supports_mmio_ext = desc->supports_mmio_ext; + xe->info.tile_mmio_ext_size = graphics_desc->tile_mmio_ext_size; xe->info.dma_mask_size = graphics_desc->dma_mask_size; xe->info.vram_flags = graphics_desc->vram_flags; diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h index bd0b0d87413e600891e69beb77f593b673a324f1..dd3546ba6f9053f8560362ba8804e5a0efdedc53 100644 --- a/drivers/gpu/drm/xe/xe_pci_types.h +++ b/drivers/gpu/drm/xe/xe_pci_types.h @@ -20,6 +20,8 @@ struct xe_graphics_desc { u64 hw_engine_mask; /* hardware engines provided by graphics IP */ + u32 tile_mmio_ext_size; /* size of MMIO extension space, per-tile */ + u8 max_remote_tiles:2; u8 has_asid:1;