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Generally the C-state latency is provided by the _CST method or FADT but some OEM platforms using AMD Picasso, Renoir, Van Gogh, and Cezanne set the C2 latency greater than C3's which causes the C2 state to be skipped. That will block the core entering PC6, which prevents s0ix working properly on Linux systems. In other operating systems the latency values are not validated and this does not cause problems by skipping states. To avoid this issue happening on Linux, detect when latencies are not an arithmetic progression and sort them. Link: 026d186e Link: drm/amd#1230 (comment 712174) Suggested-by: Prike Liang <Prike.Liang@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Change-Id: Ibf87933976385a263f8838296b01a7db2c9bc0d8
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