smu_v11_0.c 56.8 KB
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/*
 * Copyright 2019 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include <linux/firmware.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/reboot.h>
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#define SMU_11_0_PARTIAL_PPTABLE
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#define SWSMU_CODE_LAYER_L3
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#include "amdgpu.h"
#include "amdgpu_smu.h"
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#include "atomfirmware.h"
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#include "amdgpu_atomfirmware.h"
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#include "amdgpu_atombios.h"
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#include "smu_v11_0.h"
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#include "soc15_common.h"
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#include "atom.h"
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#include "amdgpu_ras.h"
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#include "smu_cmn.h"
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#include "asic_reg/thm/thm_11_0_2_offset.h"
#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
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#include "asic_reg/mp/mp_11_0_offset.h"
#include "asic_reg/mp/mp_11_0_sh_mask.h"
#include "asic_reg/smuio/smuio_11_0_0_offset.h"
#include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
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/*
 * DO NOT use these for err/warn/info/debug messages.
 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
 * They are more MGPU friendly.
 */
#undef pr_err
#undef pr_warn
#undef pr_info
#undef pr_debug

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MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
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MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
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MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
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MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
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MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
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MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
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MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
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#define SMU11_VOLTAGE_SCALE 4
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#define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms

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#define LINK_WIDTH_MAX				6
#define LINK_SPEED_MAX				3

#define smnPCIE_LC_LINK_WIDTH_CNTL		0x11140288
#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
#define smnPCIE_LC_SPEED_CNTL			0x11140290
#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE

static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
static int link_speed[] = {25, 50, 80, 160};

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int smu_v11_0_init_microcode(struct smu_context *smu)
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{
	struct amdgpu_device *adev = smu->adev;
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	const char *chip_name;
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	char fw_name[SMU_FW_NAME_LEN];
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	int err = 0;
	const struct smc_firmware_header_v1_0 *hdr;
	const struct common_firmware_header *header;
	struct amdgpu_firmware_info *ucode = NULL;
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	if (amdgpu_sriov_vf(adev) &&
			((adev->asic_type == CHIP_NAVI12) ||
			 (adev->asic_type == CHIP_SIENNA_CICHLID)))
		return 0;

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	switch (adev->asic_type) {
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	case CHIP_ARCTURUS:
		chip_name = "arcturus";
		break;
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	case CHIP_NAVI10:
		chip_name = "navi10";
		break;
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	case CHIP_NAVI14:
		chip_name = "navi14";
		break;
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	case CHIP_NAVI12:
		chip_name = "navi12";
		break;
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	case CHIP_SIENNA_CICHLID:
		chip_name = "sienna_cichlid";
		break;
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	case CHIP_NAVY_FLOUNDER:
		chip_name = "navy_flounder";
		break;
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	case CHIP_DIMGREY_CAVEFISH:
		chip_name = "dimgrey_cavefish";
		break;
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	default:
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		dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
		return -EINVAL;
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	}

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);

	err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
	if (err)
		goto out;
	err = amdgpu_ucode_validate(adev->pm.fw);
	if (err)
		goto out;

	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
	amdgpu_ucode_print_smc_hdr(&hdr->header);
	adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);

	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
		ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
		ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
		ucode->fw = adev->pm.fw;
		header = (const struct common_firmware_header *)ucode->fw->data;
		adev->firmware.fw_size +=
			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
	}

out:
	if (err) {
		DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
			  fw_name);
		release_firmware(adev->pm.fw);
		adev->pm.fw = NULL;
	}
	return err;
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}

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void smu_v11_0_fini_microcode(struct smu_context *smu)
{
	struct amdgpu_device *adev = smu->adev;

	release_firmware(adev->pm.fw);
	adev->pm.fw = NULL;
	adev->pm.fw_version = 0;
}

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int smu_v11_0_load_microcode(struct smu_context *smu)
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{
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	struct amdgpu_device *adev = smu->adev;
	const uint32_t *src;
	const struct smc_firmware_header_v1_0 *hdr;
	uint32_t addr_start = MP1_SRAM;
	uint32_t i;
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	uint32_t smc_fw_size;
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	uint32_t mp1_fw_flags;

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	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
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	src = (const uint32_t *)(adev->pm.fw->data +
		le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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	smc_fw_size = hdr->header.ucode_size_bytes;
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	for (i = 1; i < smc_fw_size/4 - 1; i++) {
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		WREG32_PCIE(addr_start, src[i]);
		addr_start += 4;
	}

	WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
		1 & MP1_SMN_PUB_CTRL__RESET_MASK);
	WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
		1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);

	for (i = 0; i < adev->usec_timeout; i++) {
		mp1_fw_flags = RREG32_PCIE(MP1_Public |
			(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
		if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
			MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
			break;
		udelay(1);
	}

	if (i == adev->usec_timeout)
		return -ETIME;

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	return 0;
}

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int smu_v11_0_check_fw_status(struct smu_context *smu)
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{
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	struct amdgpu_device *adev = smu->adev;
	uint32_t mp1_fw_flags;

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	mp1_fw_flags = RREG32_PCIE(MP1_Public |
				   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
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	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
	    MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
		return 0;
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	return -EIO;
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}

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int smu_v11_0_check_fw_version(struct smu_context *smu)
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{
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	struct amdgpu_device *adev = smu->adev;
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	uint32_t if_version = 0xff, smu_version = 0xff;
	uint16_t smu_major;
	uint8_t smu_minor, smu_debug;
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	int ret = 0;

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	ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
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	if (ret)
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		return ret;
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	smu_major = (smu_version >> 16) & 0xffff;
	smu_minor = (smu_version >> 8) & 0xff;
	smu_debug = (smu_version >> 0) & 0xff;
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	if (smu->is_apu)
		adev->pm.fw_version = smu_version;
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	switch (smu->adev->asic_type) {
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	case CHIP_ARCTURUS:
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		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
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		break;
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	case CHIP_NAVI10:
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		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
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		break;
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	case CHIP_NAVI12:
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		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
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		break;
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	case CHIP_NAVI14:
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		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
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		break;
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	case CHIP_SIENNA_CICHLID:
		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
		break;
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	case CHIP_NAVY_FLOUNDER:
		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
		break;
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	case CHIP_VANGOGH:
		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
		break;
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	case CHIP_DIMGREY_CAVEFISH:
		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
		break;
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	default:
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		dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
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		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
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		break;
	}

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	/*
	 * 1. if_version mismatch is not critical as our fw is designed
	 * to be backward compatible.
	 * 2. New fw usually brings some optimizations. But that's visible
	 * only on the paired driver.
	 * Considering above, we just leave user a warning message instead
	 * of halt driver loading.
	 */
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	if (if_version != smu->smc_driver_if_version) {
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		dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
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			"smu fw version = 0x%08x (%d.%d.%d)\n",
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			smu->smc_driver_if_version, if_version,
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			smu_version, smu_major, smu_minor, smu_debug);
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		dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
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	}

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	return ret;
}

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static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
{
	struct amdgpu_device *adev = smu->adev;
	uint32_t ppt_offset_bytes;
	const struct smc_firmware_header_v2_0 *v2;

	v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;

	ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
	*size = le32_to_cpu(v2->ppt_size_bytes);
	*table = (uint8_t *)v2 + ppt_offset_bytes;

	return 0;
}

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static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
				      uint32_t *size, uint32_t pptable_id)
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{
	struct amdgpu_device *adev = smu->adev;
	const struct smc_firmware_header_v2_1 *v2_1;
	struct smc_soft_pptable_entry *entries;
	uint32_t pptable_count = 0;
	int i = 0;

	v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
	entries = (struct smc_soft_pptable_entry *)
		((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
	pptable_count = le32_to_cpu(v2_1->pptable_count);
	for (i = 0; i < pptable_count; i++) {
		if (le32_to_cpu(entries[i].id) == pptable_id) {
			*table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
			*size = le32_to_cpu(entries[i].ppt_size_bytes);
			break;
		}
	}

	if (i == pptable_count)
		return -EINVAL;

	return 0;
}

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int smu_v11_0_setup_pptable(struct smu_context *smu)
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{
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	struct amdgpu_device *adev = smu->adev;
	const struct smc_firmware_header_v1_0 *hdr;
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	int ret, index;
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	uint32_t size = 0;
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	uint16_t atom_table_size;
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	uint8_t frev, crev;
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	void *table;
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	uint16_t version_major, version_minor;

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	if (!amdgpu_sriov_vf(adev)) {
		hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
		version_major = le16_to_cpu(hdr->header.header_version_major);
		version_minor = le16_to_cpu(hdr->header.header_version_minor);
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		if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
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			dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
			switch (version_minor) {
			case 0:
				ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
				break;
			case 1:
				ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
								smu->smu_table.boot_values.pp_table_id);
				break;
			default:
				ret = -EINVAL;
				break;
			}
			if (ret)
				return ret;
			goto out;
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		}
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	}
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	dev_info(adev->dev, "use vbios provided pptable\n");
	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
						powerplayinfo);

	ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
						(uint8_t **)&table);
	if (ret)
		return ret;
	size = atom_table_size;

out:
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	if (!smu->smu_table.power_play_table)
		smu->smu_table.power_play_table = table;
	if (!smu->smu_table.power_play_table_size)
		smu->smu_table.power_play_table_size = size;
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	return 0;
}

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int smu_v11_0_init_smc_tables(struct smu_context *smu)
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{
	struct smu_table_context *smu_table = &smu->smu_table;
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	struct smu_table *tables = smu_table->tables;
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	int ret = 0;
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	smu_table->driver_pptable =
		kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
	if (!smu_table->driver_pptable) {
		ret = -ENOMEM;
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		goto err0_out;
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	}

	smu_table->max_sustainable_clocks =
		kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
	if (!smu_table->max_sustainable_clocks) {
		ret = -ENOMEM;
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		goto err1_out;
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	}

	/* Arcturus does not support OVERDRIVE */
	if (tables[SMU_TABLE_OVERDRIVE].size) {
		smu_table->overdrive_table =
			kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
		if (!smu_table->overdrive_table) {
			ret = -ENOMEM;
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			goto err2_out;
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		}

		smu_table->boot_overdrive_table =
			kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
		if (!smu_table->boot_overdrive_table) {
			ret = -ENOMEM;
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			goto err3_out;
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		}
	}
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	return 0;
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err3_out:
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	kfree(smu_table->overdrive_table);
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err2_out:
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	kfree(smu_table->max_sustainable_clocks);
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err1_out:
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	kfree(smu_table->driver_pptable);
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err0_out:
	return ret;
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}

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int smu_v11_0_fini_smc_tables(struct smu_context *smu)
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{
	struct smu_table_context *smu_table = &smu->smu_table;
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	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
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	kfree(smu_table->gpu_metrics_table);
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	kfree(smu_table->boot_overdrive_table);
	kfree(smu_table->overdrive_table);
	kfree(smu_table->max_sustainable_clocks);
	kfree(smu_table->driver_pptable);
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	kfree(smu_table->clocks_table);
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	smu_table->gpu_metrics_table = NULL;
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	smu_table->boot_overdrive_table = NULL;
	smu_table->overdrive_table = NULL;
	smu_table->max_sustainable_clocks = NULL;
	smu_table->driver_pptable = NULL;
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	smu_table->clocks_table = NULL;
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	kfree(smu_table->hardcode_pptable);
	smu_table->hardcode_pptable = NULL;

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	kfree(smu_table->metrics_table);
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	kfree(smu_table->watermarks_table);
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	smu_table->metrics_table = NULL;
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	smu_table->watermarks_table = NULL;
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	smu_table->metrics_time = 0;
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	kfree(smu_dpm->dpm_context);
	kfree(smu_dpm->golden_dpm_context);
	kfree(smu_dpm->dpm_current_power_state);
	kfree(smu_dpm->dpm_request_power_state);
	smu_dpm->dpm_context = NULL;
	smu_dpm->golden_dpm_context = NULL;
	smu_dpm->dpm_context_size = 0;
	smu_dpm->dpm_current_power_state = NULL;
	smu_dpm->dpm_request_power_state = NULL;

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	return 0;
}
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int smu_v11_0_init_power(struct smu_context *smu)
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{
	struct smu_power_context *smu_power = &smu->smu_power;
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	size_t size = smu->adev->asic_type == CHIP_VANGOGH ?
			sizeof(struct smu_11_5_power_context) :
			sizeof(struct smu_11_0_power_context);
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	smu_power->power_context = kzalloc(size, GFP_KERNEL);
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	if (!smu_power->power_context)
		return -ENOMEM;
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	smu_power->power_context_size = size;
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	return 0;
}

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int smu_v11_0_fini_power(struct smu_context *smu)
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{
	struct smu_power_context *smu_power = &smu->smu_power;

	kfree(smu_power->power_context);
	smu_power->power_context = NULL;
	smu_power->power_context_size = 0;

	return 0;
}

500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
					    uint8_t clk_id,
					    uint8_t syspll_id,
					    uint32_t *clk_freq)
{
	struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
	struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
	int ret, index;

	input.clk_id = clk_id;
	input.syspll_id = syspll_id;
	input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
	index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
					    getsmuclockinfo);

	ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
					(uint32_t *)&input);
	if (ret)
		return -EINVAL;

	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
	*clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;

	return 0;
}

526
527
528
529
530
531
532
533
534
535
536
537
int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
{
	int ret, index;
	uint16_t size;
	uint8_t frev, crev;
	struct atom_common_table_header *header;
	struct atom_firmware_info_v3_3 *v_3_3;
	struct atom_firmware_info_v3_1 *v_3_1;

	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
					    firmwareinfo);

538
	ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
539
540
541
542
543
				      (uint8_t **)&header);
	if (ret)
		return ret;

	if (header->format_revision != 3) {
544
		dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
		return -EINVAL;
	}

	switch (header->content_revision) {
	case 0:
	case 1:
	case 2:
		v_3_1 = (struct atom_firmware_info_v3_1 *)header;
		smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
		smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
		smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
		smu->smu_table.boot_values.socclk = 0;
		smu->smu_table.boot_values.dcefclk = 0;
		smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
		smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
		smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
		smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
		smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
		smu->smu_table.boot_values.pp_table_id = 0;
564
		smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
		break;
	case 3:
	default:
		v_3_3 = (struct atom_firmware_info_v3_3 *)header;
		smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
		smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
		smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
		smu->smu_table.boot_values.socclk = 0;
		smu->smu_table.boot_values.dcefclk = 0;
		smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
		smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
		smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
		smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
		smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
		smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
580
		smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
581
582
	}

583
584
585
	smu->smu_table.boot_values.format_revision = header->format_revision;
	smu->smu_table.boot_values.content_revision = header->content_revision;

586
587
588
589
	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
					 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
					 (uint8_t)0,
					 &smu->smu_table.boot_values.socclk);
590

591
592
593
594
	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
					 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
					 (uint8_t)0,
					 &smu->smu_table.boot_values.dcefclk);
595

596
597
598
599
	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
					 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
					 (uint8_t)0,
					 &smu->smu_table.boot_values.eclk);
600

601
602
603
604
	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
					 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
					 (uint8_t)0,
					 &smu->smu_table.boot_values.vclk);
605

606
607
608
609
	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
					 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
					 (uint8_t)0,
					 &smu->smu_table.boot_values.dclk);
610

611
	if ((smu->smu_table.boot_values.format_revision == 3) &&
612
613
614
615
616
	    (smu->smu_table.boot_values.content_revision >= 2))
		smu_v11_0_atom_get_smu_clockinfo(smu->adev,
						 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
						 (uint8_t)SMU11_SYSPLL1_2_ID,
						 &smu->smu_table.boot_values.fclk);
617

618
619
620
621
622
	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
					 (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
					 (uint8_t)SMU11_SYSPLL3_1_ID,
					 &smu->smu_table.boot_values.lclk);

623
624
625
	return 0;
}

626
int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
627
628
629
630
631
632
633
634
635
636
{
	struct smu_table_context *smu_table = &smu->smu_table;
	struct smu_table *memory_pool = &smu_table->memory_pool;
	int ret = 0;
	uint64_t address;
	uint32_t address_low, address_high;

	if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
		return ret;

637
	address = (uintptr_t)memory_pool->cpu_addr;
638
639
640
	address_high = (uint32_t)upper_32_bits(address);
	address_low  = (uint32_t)lower_32_bits(address);

641
	ret = smu_cmn_send_smc_msg_with_param(smu,
642
					  SMU_MSG_SetSystemVirtualDramAddrHigh,
643
644
					  address_high,
					  NULL);
645
646
	if (ret)
		return ret;
647
	ret = smu_cmn_send_smc_msg_with_param(smu,
648
					  SMU_MSG_SetSystemVirtualDramAddrLow,
649
650
					  address_low,
					  NULL);
651
652
653
654
655
656
657
	if (ret)
		return ret;

	address = memory_pool->mc_address;
	address_high = (uint32_t)upper_32_bits(address);
	address_low  = (uint32_t)lower_32_bits(address);

658
	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
659
					  address_high, NULL);
660
661
	if (ret)
		return ret;
662
	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
663
					  address_low, NULL);
664
665
	if (ret)
		return ret;
666
	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
667
					  (uint32_t)memory_pool->size, NULL);
668
669
670
671
672
673
	if (ret)
		return ret;

	return ret;
}

674
int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
675
676
677
{
	int ret;

678
	ret = smu_cmn_send_smc_msg_with_param(smu,
679
					  SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
680
	if (ret)
681
		dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
682
683
684
685

	return ret;
}

686
687
688
689
690
691
int smu_v11_0_set_driver_table_location(struct smu_context *smu)
{
	struct smu_table *driver_table = &smu->smu_table.driver_table;
	int ret = 0;

	if (driver_table->mc_address) {
692
		ret = smu_cmn_send_smc_msg_with_param(smu,
693
				SMU_MSG_SetDriverDramAddrHigh,
694
695
				upper_32_bits(driver_table->mc_address),
				NULL);
696
		if (!ret)
697
			ret = smu_cmn_send_smc_msg_with_param(smu,
698
				SMU_MSG_SetDriverDramAddrLow,
699
700
				lower_32_bits(driver_table->mc_address),
				NULL);
701
702
703
704
705
	}

	return ret;
}

706
int smu_v11_0_set_tool_table_location(struct smu_context *smu)
707
708
{
	int ret = 0;
709
	struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
710
711

	if (tool_table->mc_address) {
712
		ret = smu_cmn_send_smc_msg_with_param(smu,
713
				SMU_MSG_SetToolsDramAddrHigh,
714
715
				upper_32_bits(tool_table->mc_address),
				NULL);
716
		if (!ret)
717
			ret = smu_cmn_send_smc_msg_with_param(smu,
718
				SMU_MSG_SetToolsDramAddrLow,
719
720
				lower_32_bits(tool_table->mc_address),
				NULL);
721
722
723
724
725
	}

	return ret;
}

726
int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
727
{
728
729
	struct amdgpu_device *adev = smu->adev;

730
731
732
733
734
	/* Navy_Flounder/Dimgrey_Cavefish do not support to change
	 * display num currently
	 */
	if (adev->asic_type >= CHIP_NAVY_FLOUNDER &&
	    adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
735
		return 0;
736

737
738
739
740
	return smu_cmn_send_smc_msg_with_param(smu,
					       SMU_MSG_NumOfDisplays,
					       count,
					       NULL);
741
742
}

743

744
int smu_v11_0_set_allowed_mask(struct smu_context *smu)
745
746
747
748
749
750
{
	struct smu_feature *feature = &smu->smu_feature;
	int ret = 0;
	uint32_t feature_mask[2];

	if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
751
		goto failed;
752
753
754

	bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);

755
	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
756
					  feature_mask[1], NULL);
757
	if (ret)
758
		goto failed;
759

760
	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
761
					  feature_mask[0], NULL);
762
	if (ret)
763
		goto failed;
764

765
failed:
766
767
768
	return ret;
}

769
int smu_v11_0_system_features_control(struct smu_context *smu,
770
					     bool en)
771
772
773
774
775
{
	struct smu_feature *feature = &smu->smu_feature;
	uint32_t feature_mask[2];
	int ret = 0;

776
	ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
777
				     SMU_MSG_DisableAllSmuFeatures), NULL);
778
779
780
	if (ret)
		return ret;

781
782
783
	bitmap_zero(feature->enabled, feature->feature_num);
	bitmap_zero(feature->supported, feature->feature_num);

784
	if (en) {
785
		ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
786
787
788
789
790
791
792
793
		if (ret)
			return ret;

		bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
			    feature->feature_num);
		bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
			    feature->feature_num);
	}
794
795
796
797

	return ret;
}

798
int smu_v11_0_notify_display_change(struct smu_context *smu)
799
800
801
{
	int ret = 0;

802
	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
803
	    smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
804
		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
805
806
807
808

	return ret;
}

809
810
static int
smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
811
				    enum smu_clk_type clock_select)
812
813
{
	int ret = 0;
814
	int clk_id;
815

816
817
	if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
	    (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
818
819
		return 0;

820
821
822
	clk_id = smu_cmn_to_asic_specific_index(smu,
						CMN2ASIC_MAPPING_CLK,
						clock_select);
823
824
825
	if (clk_id < 0)
		return -EINVAL;

826
	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
827
					  clk_id << 16, clock);
828
	if (ret) {
829
		dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
830
831
832
833
834
835
836
		return ret;
	}

	if (*clock != 0)
		return 0;

	/* if DC limit is zero, return AC limit */
837
	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
838
					  clk_id << 16, clock);
839
	if (ret) {
840
		dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
841
842
843
		return ret;
	}

844
	return 0;
845
846
}

847
int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
848
{
849
850
	struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
			smu->smu_table.max_sustainable_clocks;
851
852
853
854
855
856
857
858
859
	int ret = 0;

	max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
	max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
	max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
	max_sustainable_clocks->display_clock = 0xFFFFFFFF;
	max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
	max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;

860
	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
861
862
		ret = smu_v11_0_get_max_sustainable_clock(smu,
							  &(max_sustainable_clocks->uclock),
863
							  SMU_UCLK);
864
		if (ret) {
865
			dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
866
867
868
869
870
			       __func__);
			return ret;
		}
	}

871
	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
872
873
		ret = smu_v11_0_get_max_sustainable_clock(smu,
							  &(max_sustainable_clocks->soc_clock),
874
							  SMU_SOCCLK);
875
		if (ret) {
876
			dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
877
878
879
880
881
			       __func__);
			return ret;
		}
	}

882
	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
883
884
		ret = smu_v11_0_get_max_sustainable_clock(smu,
							  &(max_sustainable_clocks->dcef_clock),
885
							  SMU_DCEFCLK);
886
		if (ret) {
887
			dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
888
889
890
891
892
893
			       __func__);
			return ret;
		}

		ret = smu_v11_0_get_max_sustainable_clock(smu,
							  &(max_sustainable_clocks->display_clock),
894
							  SMU_DISPCLK);
895
		if (ret) {
896
			dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
897
898
899
900
901
			       __func__);
			return ret;
		}
		ret = smu_v11_0_get_max_sustainable_clock(smu,
							  &(max_sustainable_clocks->phy_clock),
902
							  SMU_PHYCLK);
903
		if (ret) {
904
			dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
905
906
907
908
909
			       __func__);
			return ret;
		}
		ret = smu_v11_0_get_max_sustainable_clock(smu,
							  &(max_sustainable_clocks->pixel_clock),
910
							  SMU_PIXCLK);
911
		if (ret) {
912
			dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
913
914
915
916
917
918
919
920
921
922
923
			       __func__);
			return ret;
		}
	}

	if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
		max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;

	return 0;
}

924
925
926
927
928
929
int smu_v11_0_get_current_power_limit(struct smu_context *smu,
				      uint32_t *power_limit)
{
	int power_src;
	int ret = 0;

930
	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
931
932
		return -EINVAL;

933
934
	power_src = smu_cmn_to_asic_specific_index(smu,
					CMN2ASIC_MAPPING_PWR,
935
936
937
					smu->adev->pm.ac_power ?
					SMU_POWER_SOURCE_AC :
					SMU_POWER_SOURCE_DC);
938
939
940
	if (power_src < 0)
		return -EINVAL;

941
942
943
944
	/*
	 * BIT 24-31: ControllerId (only PPT0 is supported for now)
	 * BIT 16-23: PowerSource
	 */
945
	ret = smu_cmn_send_smc_msg_with_param(smu,
946
					  SMU_MSG_GetPptLimit,
947
					  (0 << 24) | (power_src << 16),
948
949
950
951
952
953
954
					  power_limit);
	if (ret)
		dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);

	return ret;
}

955
int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
956
{
957
	int power_src;
958
	int ret = 0;
959

960
	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
961
		dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
962
		return -EOPNOTSUPP;
963
964
	}

965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
	power_src = smu_cmn_to_asic_specific_index(smu,
					CMN2ASIC_MAPPING_PWR,
					smu->adev->pm.ac_power ?
					SMU_POWER_SOURCE_AC :
					SMU_POWER_SOURCE_DC);
	if (power_src < 0)
		return -EINVAL;

	/*
	 * BIT 24-31: ControllerId (only PPT0 is supported for now)
	 * BIT 16-23: PowerSource
	 * BIT 0-15: PowerLimit
	 */
	n &= 0xFFFF;
	n |= 0 << 24;
	n |= (power_src) << 16;
981
	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
982
	if (ret) {
983
		dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
984
985
		return ret;
	}
986
987

	smu->current_power_limit = n;
988

989
	return 0;
990
991
}

992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
{
	return smu_cmn_send_smc_msg(smu,
				SMU_MSG_ReenableAcDcInterrupt,
				NULL);
}

static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
{
	int ret = 0;

	if (smu->dc_controlled_by_gpio &&
	    smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
		ret = smu_v11_0_ack_ac_dc_interrupt(smu);

	return ret;
}

1010
1011
1012
1013
1014
1015
void smu_v11_0_interrupt_work(struct smu_context *smu)
{
	if (smu_v11_0_ack_ac_dc_interrupt(smu))
		dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
}

1016
int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1017
{
1018
	int ret = 0;
1019

1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
	if (smu->smu_table.thermal_controller_type) {
		ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
		if (ret)
			return ret;
	}

	/*
	 * After init there might have been missed interrupts triggered
	 * before driver registers for interrupt (Ex. AC/DC).
	 */
	return smu_v11_0_process_pending_interrupt(smu);
1031
1032
}

1033
int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
1034
{
1035
	return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1036
1037
}

1038
1039
1040
1041
1042
static uint16_t convert_to_vddc(uint8_t vid)
{
	return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
}

1043
int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
{
	struct amdgpu_device *adev = smu->adev;
	uint32_t vdd = 0, val_vid = 0;

	if (!value)
		return -EINVAL;
	val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
		SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
		SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;

	vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);

	*value = vdd;

	return 0;

}

1062
int
1063
1064
1065
1066
1067
1068
smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
					struct pp_display_clock_request
					*clock_req)
{
	enum amd_pp_clock_type clk_type = clock_req->clock_type;
	int ret = 0;
1069
	enum smu_clk_type clk_select = 0;
1070
1071
	uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;