- 08 Nov, 2022 2 commits
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Yusuf Khan authored
Signed-off-by:
Yusuf Khan <yusisamerican@gmail.com> Reviewed-by:
Karol Herbst <kherbst@redhat.com> -
Yusuf Khan authored
So that we dont expose certain options for nir_to_tgsi Signed-off-by:
Yusuf Khan <yusiamerican@gmail.com> Reviewed-by:
Karol Herbst <kherbst@redhat.com>
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- 27 Oct, 2022 11 commits
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Replace tabs with spaces. Fix up function pointer calls (don't use the old style (*foo)(arg) syntax). Signed-off-by:
Brian Paul <brianp@vmware.com> Reviewed-by:
Adam Jackson <ajax@redhat.com> Part-of: <mesa/mesa!19329>
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Replace tabs w/ spaces, remove trailing whitespace. Signed-off-by:
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Replace tabs with spaces. Rename __ATTRIB macro to SIMPLE_CASE to be a bit more readable. NFC. Signed-off-by:
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Replace tabs with spaces, fix indentation. Move 'format' var decl and type (it's an integer array index, not actually a mesa format). NFC. Signed-off-by:
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Signed-off-by:
Karol Herbst <kherbst@redhat.com>
Part-of: <mesa/mesa!19256> -
Signed-off-by:
Yiwei Zhang <zzyiwei@chromium.org> Part-of: <mesa/mesa!19285>
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Signed-off-by:
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Signed-off-by:
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This brings in: - VK_KHR_push_descriptor - VK_EXT_depth_clip_control - VK_EXT_primitives_generated_query Signed-off-by:
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Fixes: 4d80ccbf ("venus: Enable VK_KHR_format_feature_flags2") Signed-off-by:
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This is some left over from prior 1.3 effort. Signed-off-by:
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- 26 Oct, 2022 27 commits
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Change the function parameters to 32-bit. Reviewed-by:
Emma Anholt <emma@anholt.net> Reviewed-by:
Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <mesa/mesa!19291> -
Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: 
Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <mesa/mesa!19320> -
Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <mesa/mesa!19320> -
Using the wl_drm protocol we can check whether the compositor uses the same GPU as the application. This allows to run vulkan applications using a DG2 GPU with the compositor using another card. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Simon Ser <contact@emersion.fr> Part-of: <!19224>
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So that we can provide that information to WSI if it asks for it immediately. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <mesa/mesa!19224> -
We can't have streamout and mesh enabled at the same time. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ef04caea
("anv: Implement Mesh Shading pipeline")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <mesa/mesa!19323> -
Part-of: <mesa/mesa!19192>
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Part-of: <mesa/mesa!19192>
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some apps (most notably Wolfenstein: The New Order) have broken multi-context buffer usage in which one context will attempt to write to a buffer while another context holds unflushed usage, and the unflushed context will never flush until the buffer write completes it's impossible to handle this scenario correctly without deadlocking, so add some handling to try waiting and then yolo the buffer write if a deadlock would occur Part-of: <mesa/mesa!19141>
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It will already short-circuit if the number of components matches. Reviewed-by:
Karol Herbst <kherbst@redhat.com>
Reviewed-by: 
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!19301> -
Reviewed-by:
Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!19301> -
nir_shader_lower_instructions is overkill and this makes the pass generally easier to understand. Reviewed-by:
Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!19301> -
Reviewed-by:
Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!19301> -
The flush_resources recorded in the context need to stay alive until the context is flushed, at which point additional resolve operations are done to those resources. While the backing BO is alive due to being referenced in the cmdstream, the resource might already be destroyed at this point. Keep a reference to the resource to make sure it is still available at context flush time. Fixes: 7b9d8d19 ("etnaviv: flush used render buffers on context flush when neccessary") Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <mesa/mesa!19280> -
Avoids hang running rendercheck -t cacomposite -f a8r8g8b8 via glamor on Navi 14. Closes: mesa/mesa#7167 Fixes: 7833c513 ("winsys/amdgpu: use cached GTT for command buffers and don't set the 32BIT flag") Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <mesa/mesa!19276>
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SoroushIMG authored
So far, only IMG drivers cannot handle out of bounds layer values. Ideally, a vulkan extension will be drafted to detail this behavior. But for now if KHR-GL46.texture_cube_map_array.color_depth_attachments fails, then needs_sanitised_layer is probably needed. Part-of: <!19163>
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SoroushIMG authored
GL spec forces driver to ignore gl_Layer, if layered rendering is not enabled. Since vulkan doesn't have the same bavior, emulate this by forcing gl_Layer to 0, based on driver internal state. This was seen as failure in KHR-GL46.texture_cube_map_array.color_depth_attachments Part-of: <!19163>
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SoroushIMG authored
This state is needed to make sure gl_Layer values are set to 0, when the framebuffer is not layered accorfing to GL spec. Specifically Section 9.8 Layered Framebuffers of GL46 spec: A layer number written by a geometry shader has no effect if the framebuffer is not layered. Vulkan has no carve out for this, so zink must handle this by sanitising gl_Layer (next commit in the series). Part-of: <!19163>
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SoroushIMG authored
Now that all gfx pipelines share the same push constant layout, create a screen wide push const only layout that is compatible with all future programs. This layout will be used to update push constant values, so that the update can happen at any point before draw call. Part-of: <!19163>
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SoroushIMG authored
move the hashing to the caller, since it's not related to this. Additionally, remove dependance on zink_program argument. Part-of: <mesa/mesa!19163>
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SoroushIMG authored
Part-of: <!19163>
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SoroushIMG authored
Extend vs_pushconst structure to all gfx stages and make sure, the push constant memory layout is defined in one place and is therefore always correct. No functional change, but should make adding new members to zink_*_push_constant easier. Part-of: <!19163>
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SoroushIMG authored
Part-of: <mesa/mesa!19163>
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On Q2RTX shaders : Instructions in all programs: 31039 -> 26150 (-15.8%) SENDs in all programs: 1587 -> 1148 (-27.7%) Loops in all programs: 4 -> 4 (+0.0%) Cycles in all programs: 420218 -> 392179 (-6.7%) Spills in all programs: 157 -> 132 (-15.9%) Fills in all programs: 337 -> 262 (-22.3%) Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com> Part-of: <!16556>
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On Q2RTX shaders : MaxWaves: 62 -> 69 (+11.29%) Instrs: 41626 -> 41575 (-0.12%); split: -0.27%, +0.15% CodeSize: 224960 -> 223740 (-0.54%); split: -0.62%, +0.08% VGPRs: 800 -> 704 (-12.00%) Scratch: 75776 -> 70656 (-6.76%) Latency: 922219 -> 977997 (+6.05%) InvThroughput: 212154 -> 201746 (-4.91%); split: -5.54%, +0.64% VClause: 1120 -> 1155 (+3.12%); split: -1.88%, +5.00% SClause: 1148 -> 1144 (-0.35%); split: -0.70%, +0.35% Copies: 5840 -> 5788 (-0.89%); split: -0.94%, +0.05% PreVGPRs: 753 -> 651 (-13.55%) Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: -
In particular when using scratch_base_ptr Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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The intel backend compiler is not dealing with the scratch loads emitted by this pass very well. There are 2 reasons for this : - all loads are at the top of the shader - the loads are global load intrinsics (cannot be differentiated from ssbo loads for example) This leads the backend to generate ridiculous amount of spills. To help a bit (actually quite a lot), we can move the scratch loads in the blocks where they're needed, using the dominance information. Quite often that also ends up moving loads in a block that might not be reached by all the lanes, so we're potentially avoiding some loads. Signed-off-by:Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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