Commit 7d4c9356 authored by Marek Olšák's avatar Marek Olšák
Browse files

radeonsi: initialize textures using DCC to black when possible


Reviewed-by: default avatarNicolai Hähnle <nicolai.haehnle@amd.com>
parent 3361305f
......@@ -34,15 +34,6 @@ enum {
SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
};
enum si_dcc_clear_code
{
DCC_CLEAR_COLOR_0000 = 0x00000000,
DCC_CLEAR_COLOR_0001 = 0x40404040,
DCC_CLEAR_COLOR_1110 = 0x80808080,
DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
DCC_CLEAR_COLOR_REG = 0x20202020,
};
static void si_alloc_separate_cmask(struct si_screen *sscreen,
struct si_texture *tex)
{
......
......@@ -111,6 +111,16 @@
#define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
#define SI_RESOURCE_FLAG_SO_FILLED_SIZE (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
enum si_clear_code
{
DCC_CLEAR_COLOR_0000 = 0x00000000,
DCC_CLEAR_COLOR_0001 = 0x40404040,
DCC_CLEAR_COLOR_1110 = 0x80808080,
DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
DCC_CLEAR_COLOR_REG = 0x20202020,
DCC_UNCOMPRESSED = 0xFFFFFFFF,
};
/* Debug flags. */
enum {
/* Shader logging options: */
......
......@@ -1242,10 +1242,59 @@ si_texture_create_object(struct pipe_screen *screen,
/* Initialize DCC only if the texture is not being imported. */
if (!buf && tex->dcc_offset) {
si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
tex->dcc_offset,
tex->surface.dcc_size,
0xFFFFFFFF);
/* Clear DCC to black for all tiles with DCC enabled.
*
* This fixes corruption in 3DMark Slingshot Extreme, which
* uses uninitialized textures, causing corruption.
*/
if (tex->surface.num_dcc_levels == tex->buffer.b.b.last_level + 1 &&
tex->buffer.b.b.nr_samples <= 2) {
/* Simple case - all tiles have DCC enabled. */
si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
tex->dcc_offset,
tex->surface.dcc_size,
DCC_CLEAR_COLOR_0000);
} else if (sscreen->info.chip_class >= GFX9) {
/* Clear to uncompressed. Clearing this to black is complicated. */
si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
tex->dcc_offset,
tex->surface.dcc_size,
DCC_UNCOMPRESSED);
} else {
/* GFX8: Initialize mipmap levels and multisamples separately. */
if (tex->buffer.b.b.nr_samples >= 2) {
/* Clearing this to black is complicated. */
si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
tex->dcc_offset,
tex->surface.dcc_size,
DCC_UNCOMPRESSED);
} else {
/* Clear the enabled mipmap levels to black. */
unsigned size = 0;
for (unsigned i = 0; i < tex->surface.num_dcc_levels; i++) {
if (!tex->surface.u.legacy.level[i].dcc_fast_clear_size)
break;
size = tex->surface.u.legacy.level[i].dcc_offset +
tex->surface.u.legacy.level[i].dcc_fast_clear_size;
}
/* Mipmap levels with DCC. */
if (size) {
si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
tex->dcc_offset, size,
DCC_CLEAR_COLOR_0000);
}
/* Mipmap levels without DCC. */
if (size != tex->surface.dcc_size) {
si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
tex->dcc_offset + size,
tex->surface.dcc_size - size,
DCC_UNCOMPRESSED);
}
}
}
}
/* Initialize the CMASK base register value. */
......
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