nir: Don't Optimize AND'd shift bit count if not supported

Spir-v specifies shifts by values more than bit width to be undefined.
This means removing the AND by (bitwidth-1) is invalid for zink.
This opt produced ishl by constant (-1) when using soft fp64.
This caused failures in a bunch of cts cases involving fp64 like:
KHR-GL46.gpu_shader_fp64.builtin.ceil_double.

Cc: mesa-stable
Reviewed-by: Timur Kristó?f <timur.kristof@gmail.com>
Part-of: <mesa/mesa!18054>
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