- Oct 10, 2022
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Ella Stanforth authored
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- Oct 07, 2022
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Ella Stanforth authored
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Ella Stanforth authored
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Ella Stanforth authored
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- Oct 05, 2022
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Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Part-of: <mesa/mesa!18969>
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The layout calculation accidentally thought these would be stored in variables, but that's not the case. Fixes: 697ea022 Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com> Reviewed-by:
Rhys Perry <pendingchaos02@gmail.com> Part-of: <mesa/mesa!18846>
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Signed-off-by:
Brian Paul <brianp@vmware.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!18954>
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Signed-off-by:
Brian Paul <brianp@vmware.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!18954>
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Signed-off-by:
Brian Paul <brianp@vmware.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!18954>
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Consistent whitespace, move var decls to first use, add some const qualifiers, etc. Signed-off-by:
Brian Paul <brianp@vmware.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!18954>
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Ivan Briano authored
Reviewed-by:
Jason Ekstrand <jason.ekstrand@collabora.com> Part-of: <mesa/mesa!18958>
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Ivan Briano authored
Reviewed-by:
Jason Ekstrand <jason.ekstrand@collabora.com> Part-of: <mesa/mesa!18958>
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Now the state tracker's responsible to lower away for us (and the state tracker can do it correctly, our implementation is incorrect with a strict reading of the Gallium contract). Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!18658>
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Unused and now won't be used. Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <mesa/mesa!18658>
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The cso code hashes these as a block of bytes. This silences some Valgrind uninitialized memory warnings and possibly avoids creating some redundant sampler instances. Signed-off-by:
Brian Paul <brianp@vmware.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!18953>
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Rejig some dirty state checks to avoid continue and make it consistent with surrounding code. Signed-off-by:
Brian Paul <brianp@vmware.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!18953>
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Maybe the frontend should map for us in this case, but it's easy enough here: ETC2 is an extension to use undefined states from ETC1, and is backwards compatible. Reviewed-by:
Erik Faye-Lund <erik.faye-lund@collabora.com> Reviewed-by:
Adam Jackson <ajax@redhat.com> Part-of: <mesa/mesa!18957>
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Without this, the frontend would decompress them for us without even the kindness of a perf debug warning. Reviewed-by:
Erik Faye-Lund <erik.faye-lund@collabora.com> Reviewed-by:
Adam Jackson <ajax@redhat.com> Part-of: <mesa/mesa!18957>
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There is a 1-to-1 mapping from pipe to vk formats for ETC2. Reviewed-by:
Erik Faye-Lund <erik.faye-lund@collabora.com> Reviewed-by:
Adam Jackson <ajax@redhat.com> Part-of: <mesa/mesa!18957>
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You won't have a non-void channel for block formats, because "how many bits are there in the red channel" doesn't even make sense. Reviewed-by:
Adam Jackson <ajax@redhat.com> Part-of: <mesa/mesa!18957>
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The linked MR landed and fixed them. Reviewed-by:
Adam Jackson <ajax@redhat.com> Part-of: <mesa/mesa!18957>
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Like on adreno 3xx, hw binning and scissor optimizations don't work correctly together on a4xx and a5xx GPUs. Disable binning as a workaround if scissor optimizations are being used. Fixes: f68c6951 8efaae3e Signed-off-by:
Alejandro Tafalla <atafalla@dnyon.com> Reviewed-by:
Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!18925>
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Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Part-of: <mesa/mesa!18952>
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- Oct 04, 2022
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On my ppc64le machine with 32 hardware threads, this speeds up OpenArena (1920x1200) from 7.2 fps to 8.1 fps. Reviewed-by:
Emma Anholt <emma@anholt.net> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!18415>
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Render server config will soon become a mandatory requirement for venus. v2: updated DEBIAN_BASE_TAG and KERNEL_ROOTFS_TAG Signed-off-by:
Yiwei Zhang <zzyiwei@chromium.org> Reveiwed-by: Ryan Neph <ryanneph@google.com> (v1) Reveiwed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> (v1) Reviewed-by: Corentin Noël <corentin.noel@collabora.com> (v2) Part-of: <mesa/mesa!18918>
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We have the correct merged color write enable state as a local var here, use that instead of the zero cmd->state.color_write_enable. Fixes blending in many traces with ANGLE on turnip. In the process of fixing, clarify the logic a little bit. Fixes: 169e0380 ("tu: Implement VK_EXT_color_write_enable") Fixes: #7328 Part-of: <mesa/mesa!18956>
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Dave Airlie authored
These are no longer used. Reviewed-by:
Mihai Preda <mhpreda@gmail.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!18947>
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Dave Airlie authored
This uses the types to do the loads using opaque ptr interfaces. Reviewed-by:
Mihai Preda <mhpreda@gmail.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!18947>
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Dave Airlie authored
Some of the generic code tries to load from things it has no types for, mip offsets, row and image strides. Fix the interfaces to allow returning types for these. Reviewed-by:
Mihai Preda <mhpreda@gmail.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!18947>
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Dave Airlie authored
This removes the non-opaque paths from the draw/lp sampling code. Reviewed-by:
Mihai Preda <mhpreda@gmail.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!18947>
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Dave Airlie authored
This adds explicit context types wiring through the sampler code Reviewed-by:
Mihai Preda <mhpreda@gmail.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!18947>
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Dave Airlie authored
Reviewed-by:
Mihai Preda <mhpreda@gmail.com> Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Part-of: <mesa/mesa!18947>
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Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Part-of: <mesa/mesa!18942>
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Continuing the work to split i915_drm.h specific code. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Part-of: <mesa/mesa!18942>
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This will make easier to spot more places where the code can simplified after the hasvk split. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Part-of: <mesa/mesa!18942>
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Move everything that depends on i915_drm.h to its own function, in a future MR will move the parameters that are also needed by Iris to intel_device_info. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Part-of: <mesa/mesa!18942>
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Continuing the work to split i915_drm.h specific code. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Part-of: <mesa/mesa!18942>
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There is too much i915_drm.h code spread, this patch start to fix that by re-organizing engine related code. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Part-of: <mesa/mesa!18942>
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Signed-off-by:
Yiwei Zhang <zzyiwei@chromium.org> Reviewed-by:
Ryan Neph <ryanneph@google.com> Part-of: <mesa/mesa!18941>
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Part-of: <mesa/mesa!18773>
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